Samsung Electronics Co., Ltd.

Heejueng Lee

Seongjun Seo

Heung Jin Joo

Hyunseok Na

Seungwan Hong

Hyun-Seok Na

Kyungjun Shin

Yunkyu Jung

Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.

Vertical memory devices with reduced gate electrode coupling and methods of manufacturing the same

A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.

Three-dimensional semiconductor memory devices

Growing community of inventors

Suwon-si, South Korea

Heejueng Lee