Skhynix Inc.

Heeeun Choi

Ji Eun Kim

Kwang Soon Kim

Yeong Han Jeong

Hoi Ju Chung

A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

Memory apparatus and semiconductor system including the same

A memory device includes an auto error check scrub (ECS) control circuit configured to generate an auto ECS command for performing an ECS operation based on a refresh control signal. The memory device also includes a burst ECS control circuit configured to generate an internal burst ECS command for performing the ECS operation every set period based on a burst ECS command and an ECS end flag. The memory device further includes an ECS address generation circuit configured to generate an ECS address for the ECS operation by counting an input of the auto ECS command or the internal burst ECS command and to generate the ECS end flag based on a value of the ECS address.

Growing community of inventors

Icheon-si, South Korea

Heeeun Choi