Samsung Electronics Co., Ltd.

Heedon Jeong

Donghyun Kim

Heesoo Kang

Sanghyuk Hong

Jae Yup Chung

Soohun Hong

Myung Gil Kang

Changwoo Oh

Sangyoon Kim

Je-min Yoo

Jongmil Youn

Hwasung Rhee

Chiwon Cho

Woosik Kim

A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

Semiconductor device with fin field effect transistors

A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Semiconductor device including a three-dimensional channel

Semiconductor device

Semiconductor device with fin field effect transistors having different separation regions between fins in NMOS and PMOS regions

Method of fabricating semiconductor device including an etch barrier pattern

A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

Fin field effect transistors including multiple lattice constants and methods of fabricating the same

Semiconductor device and fabricating method thereof

Growing community of inventors

Hwaseong-si, South Korea

Heedon Jeong