Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Heechoul Park

Jungyong Lee

Song C Kim

Hoyeol Cho

Gregory Frederick Grohoski

Clement Fang

David Jeffrey

Myung Gyoo Won

Neil Duncan

Singrong Li

Lik Cheng

Robert Paul Masleid

Shree Kant

Jason M Hart

Jinho Kwack

Peter Normand Labrecque

Zhen Wu Liu

Lancelot Y Kwong

Xiaozhen Guo

Kuan-Yu James Lin

Thu Hanh Nguyen

Wilson Chin

Sanjaya Dharmasena

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Detection of multiple accesses to a row address of a dynamic memory within a refresh period

Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Memory bitcell with column select

Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.

Sense amp activation according to word line common point

Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.

Memory array clock gating scheme

Embodiments include systems and methods for faster memory read-out using a combined read-select circuit. A novel read-select circuit is described, which, when enabled for reading, concurrently reads its respective input line and selects its value for read-out by the circuit. This can reduce delays and unnecessary toggling resulting from separate read and select circuits. Some implementations also include a multi-global-line architecture that can reduce the number of read stages in the memory read-out circuitry, thereby further reducing read-out delays. Accordingly, embodiments can be faster and more efficient than many traditional implementations without relying on an increase in power consumption or clock speed.

Fast memory read-out

A process variation tolerant collision detection apparatus for use in detecting collisions in a multibank memory. The apparatus may receive a plurality of memory commands for execution at the multibank memory. The plurality of memory commands may be compared by an index address comparator and a bank address comparator to generate an index match signal and a bank match signal. The index match signal and the bank match signal may be analyzed by a timing correction module such that errors associated with process variation of the signals used in the system may be eliminated. Accordingly, a corrected index match signal and a corrected bank match signal may be provided to a collision detection circuit to determine whether a collision exits.

Process variation tolerant bank collision detection circuit

Circuits, methods, and systems are presented for managing current leakage in an electronic circuit. One circuit includes a keeper circuit, and a controller. The keeper circuit supplies current to a leaker circuit, which is experiencing current leakage, to compensate for the current leakage. Further, the controller provides to the keeper circuit a control signal that is based on the current leakage. The control signal has a cycle equal to the cycle of a clock signal, and the control signal is a pulse having a first value during a first period, and a second value during a second period of the pulse. The keeper circuit provides a current to the leaker circuit during the first period and the keeper circuit withholds the current to the leaker circuit during the second period, where the durations of the first period and the second period are based on the current leakage.

Adaptive timing control circuitry to address leakage

Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.

Methods and apparatuses for improving reduced power operations in embedded memory arrays

A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM.

Dynamically controlled voltage regulator for a memory

A push-pull voltage regulator configured to selectively provide power to used portions of a memory array is presented. The push-pull voltage regulator includes a voltage-up regulator, which provides a reference voltage to an SRAM array, and a voltage-down regulator, which controls removal of excess charge from the SRAM array. The voltage-down regulator consists of a plurality of amplifier stages with a plurality of inputs, a plurality of inverters, a gain amplifier, a biasing transistor, and a NMOS drainage transistor. The gate terminal of the NMOS drainage transistor is coupled to an output of the voltage-down regulator. A first output terminal of the NMOS drainage transistor coupled to an output node of the push-pull voltage regulator and a second output terminal of the NMOS drainage transistor coupled to ground. When activated, the NMOS drainage transistor transfers excess charge from the SRAM array to ground.

Voltage regulator for write/read assist circuit

A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.

Precision falling edge generator

A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Write and read assist circuit for SRAM with power recycling

A SRAM memory with a read assist circuit is presented. The read assist circuit uses bitline voltage level switches, which are connected to a low power supply and a high power supply. The bitline voltage level switches have a write operation state, a read operation state, and a standby operation state. The write operation state selectively provides the high power supply to bitlines in columns selected for a write operation, and provides the low power supply to bitlines in the remaining columns. The read operation state selectively provides the low power supply to bitlines in columns selected for the read operation, and provides the low power supply to bitlines in the other columns. The standby operation state selectively provides the low power supply to bitlines in all columns when not in the read operation state or the write operation state.

Read assist circuit of SRAM with low standby current

A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.

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San Jose, CA, United States of America

Heechoul Park