Boe Technology Group Co., Ltd.

Chongqing Boe Optoelectronics Technology Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Beijing Boe Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Heecheol Kim

Youngsuk Song

Seungjin Choi

Seongyeol Yoo

Chao Xu

Chunfang Zhang

Yan Wei

Hyun Sic Choi

Zhi Zhang

Shuai Chen

Hyunsic Choi

Yinglong Huang

Xing Dong

Jingpeng Zhao

Xue Dong

Wei Qin

Jaegeon You

Xinxing Wang

Xiuzhu Tang

Zhuo Xu

Liwei Liu

Yajie Bai

Hailong Wu

Yun Sik Im

Taoliang Tang

Shuo Li

Yunsik Im

Yuanbo Zhang

Shaoru Li

Zhenguo Tian

Lijun Xiong

Teng Chen

Yi Dan

Taeyup Min

Min Ran

Hui Li

Peng Li

Fan Yang

Kuanjun Peng

Zhiqiang Xu

Gang Chen

Xinli Ma

Shuang Hu

Ni Yang

Shang Wang

Wanpeng Teng

Zhihui Wang

Jaikwang Kim

Yanxin Wang

Yoonsung Um

Yunyun Tian

Xiaolong Liu

Yoon Sung Um

Zhijian Qi

Cheng Zuo

Yanli Zhao

Kangpeng Dang

Chulgyu Jung

Yan Xa Zhou

Peng Liang

Jungho Park

Haipeng Zhu

Yuqing Zhang

Jianbo Fu

Jai-Il Ryu

Yang He

Daoping Yu

Song Young Suk

Yoo Seong Yeol

Choi Seung Jin

Wangjing Bai

Xiaojun Zuo

Song-Young- Suk

Yoo-Seong- Yeol

Choi-Seung- Jin

Im Yun Sik

A shift register unit, configured to generate a first gate drive signal and a second gate drive signal, which includes a first control circuit, configured to control a potential of a first node; a second control circuit, configured to control a potential of a second node; a first output circuit, configured to generate the first gate drive signal based on a first voltage signal provided by a first voltage terminal under the control of the potentials of the first and second nodes, and output the first gate drive signal through a first gate drive signal output terminal, wherein the first voltage signal provided by the first voltage terminal is a high level signal; and a second output circuit, configured to generate a second gate drive signal based on a second voltage signal provided by a second voltage terminal under the control of a potential of a control node, and output the second gate drive signal through a second gate drive signal output terminal.

Pixel circuit, shift register unit, gate driving circuit and display device

A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Display panel and display device

The present disclosure provides a composite structure, including first and second structure layers which are opposite to each other and adjustment bodies. The first structure layer includes first structure bodies. The second structure layer includes second structure bodies. The first structure bodies and the second structure bodies are staggered. First connecting portions protruding toward the second structure layer are provided at predetermined positions on the first structure bodies where the first structure bodies are staggered relative to the second structure bodies, and second connecting portions protruding toward the first structure layer are provided at predetermined positions on the second structure bodies where the second structure bodies are staggered relative to the first structure bodies, and the first connecting portions and the second connection portions are staggered. The adjustment bodies are connected in a layer direction between the first connecting portions and the second connecting portions.

Composite structure

A pixel circuit includes a driving circuit, configured to drive a light-emitting element to emit light; a compensation control circuit, electrically connected to a first gate line and configured to control a control terminal of the driving circuit to be connected with a second terminal of the driving circuit under the control of a first gate drive signal provided by the first gate line; and a data writing circuit, electrically connected to a second gate line and configured to control a data voltage to be provided to a first terminal of the driving circuit under the control of a second gate drive signal provided by the second gate line. A voltage value of the first gate drive signal is substantially different from a voltage value of the second gate drive signal.

A scan driving circuit and a driving method thereof, and a display device are disclosed. The scan driving circuit includes: a control circuit, a scanning circuit group and a first processing circuit group. The control circuit is configured to generate and output a keyword signal to the first processing circuit group, to control a scan order of respective scanning circuits in the scanning circuit group; the first processing circuit group is configured to generate a scan enable signal according to the keyword signal, and output the scan enable signal to a scanning circuit corresponding to the keyword signal in the scanning circuit group.

Scan driving circuit and driving method thereof, and display device

The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.

Gate drive unit and driving method thereof and gate drive circuit

A display panel is provided. The display panel includes a first substrate faces a second substrate. The first substrate includes a plurality of first spacers and a plurality of second spacers. The second substrate includes a corresponding plurality of first protrusions and a plurality of second protrusions. A sum of a height of the first protrusion and a height of the first spacer is greater than that of the second spacer. Each of the first spacers includes at least one protrusion. A length of an orthographic projection of each protrusion on a plane of the first substrate is longer in one direction.

Display panel, display device and terminal

Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process.

Array substrate and display device

A shift register circuit includes a first circuit, M second circuits, and N third circuits. M and N are both positive integers, N is an integer multiple of M, M is greater than or equal to 2, and a quotient of N and M is greater than or equal to 2. The first circuit includes a first signal output terminal. Each second circuit includes a second signal input terminal connected to the first signal output terminal. Each third circuit includes a third signal input terminal that is connected to one of second signal input terminals of the M second circuits. A second signal output terminal of each second circuit is connected to third signal input terminals of N/M third circuits, and different second signal output terminals are connected to different third signal input terminals.

Shift register circuit and driving method therefor, and gate drive circuit and display device

A display driving circuit, a driving method thereof, and a display device are provided. The display driving circuit includes: a timing controller which is configured to acquire grayscale data of subpixels in a frame of display image row by row and output the grayscale data to the grayscale controller; a grayscale controller which is configured to receive grayscale data of each subpixel in each row of subpixels, and control at least a part of the plurality of reference grayscale voltage output terminals in the grayscale controller to output reference grayscale voltages according to the grayscale data of each subpixel in each row of subpixels; a source IC which is configured to generate a grayscale voltage according to the received reference grayscale voltages and input the grayscale voltage as a data voltage to a data line.

Display driving circuit and driving method thereof, display device

A display substrate, a manufacturing method thereof and a display device are provided, and the display substrate includes pixel units, each of the pixel units is provided with a thin film transistor, a pixel electrode and a common electrode; the pixel electrode and the common electrode are arranged in a same layer and insulated from each other, the pixel electrode includes a plurality of strip-shaped pixel sub-electrodes, the common electrode includes a plurality of strip-shaped common sub-electrodes, the plurality of strip-shaped pixel sub-electrodes () and the plurality of strip-shaped common sub-electrodes are alternately distributed, and an interval width between each pixel sub-electrode and each common sub-electrode adjacent to the pixel sub-electrode is from 1 &#x3bc;m to 5 &#x3bc;m. The display substrate is configured for solving the problem of low charging rate in large size display panels.

Display substrate, manufacturing method thereof and display device

An amplitude control main circuit, a voltage supply modular circuit, a display device, and an amplitude control method are provided. The amplitude control main circuit includes a variable resistive circuit, an output control circuit and a gate-driving-power-voltage output terminal; the output control circuit is connected to an output control terminal, a voltage input terminal, the gate-driving-power-voltage output terminal, and the variable resistive circuit, and controls, under control of the output control terminal, the gate-driving-power-voltage output terminal to be connected to the voltage input terminal directly or via the variable resistive circuit; a control terminal, a first terminal, and a second terminal of the variable resistive circuit are connected to a resistance control terminal, the output control circuit, and the gate-driving-power-voltage output terminal, respectively, and a resistance value of the variable resistive circuit is changed under control of the resistance control terminal.

Amplitude control main circuit, voltage supply modular circuit, display device and amplitude control method

An array substrate and a manufacture method thereof, a display panel and a display device. The array substrate includes pixel units. Each pixel unit includes a pixel electrode and a common electrode, which are respectively includes first pixel electrode strips and first common electrode strips that are arranged substantially in parallel in parallel in a first direction, each first common electrode strip overlaps at least one first pixel electrode strip. Each pixel unit includes at least one pixel unit sub-area, which has a sub-area symmetry axis, the first pixel electrode strip and the first common electrode strip are respectively arranged with respect to the sub-area symmetry axis symmetrically. On either side of the sub-area symmetry axis, the first common electrode strip is farther away from or closer to the sub-area symmetry axis than the at least one first pixel electrode strip that the each first common electrode strip overlaps.

Array substrate comprising a plurality of first pixel electrode strips and first common electrode strips arranged symmetrically with respect to a sub-area symmetry axis of a pixel unit sub-area and manufacture method thereof, display panel and display device

A pixel structure, a display panel and a display device are provided. The pixel structure includes: a base substrate; a plurality of gate lines; a plurality of data lines; a plurality of pixel units, each includes a pixel electrode and a common electrode; and a common electrode line connected with the common electrode, wherein, the common electrode line includes a first part extended along the row direction and a second part extended along the column direction; the first part is electrically connected with the second part; both the first part and the second part are arranged in a same layer with the plurality of data lines; and a projection of the first part on the base substrate is at least partially disposed between projections of a gate line among the plurality of gate lines which is closest to the first part and the pixel electrode on the base substrate.

Pixel structure, display panel and display device

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Beijing, China

Heecheol Kim