Samsung Electronics Co., Ltd.

Yonsei University

Heechai Kang

Seong-Ook Jung

Kyungho Ryu

Donghwan Lee

Won Seok Lee

Jong-Ryun Choi

Donghoon Jung

Suho Kim

A phase-locked loop circuit includes a first circuit, a second circuit, and a voltage down converter. The first circuit generates a first signal based on a reference signal and a feedback signal, and operates based on a first supply voltage. The second circuit generates an oscillation signal based on a second signal, generates the feedback signal by dividing the oscillation signal, and operates based on a second supply voltage lower than the first supply voltage. The voltage down converter generates the second signal by decreasing an activation voltage level of the first signal. The voltage down converter includes at least one passive element electrically connected between the first circuit and the second circuit.

Phase-locked loop circuit including voltage down converter consisting of passive element

Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

Digital DLL including skewed gate type duty correction circuit and duty correction method thereof

A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.

Clock delay circuit and delay locked loop including the same

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Seoul, South Korea

Heechai Kang