Hynix Semiconductor Inc.

Skhynix Inc.

Hee Woong Song

Tae Jin Hwang

Yong Ju Kim

Hyung Soo Kim

Ic Su Oh

Ji Wang Lee

Hae Rang Choi

Sung Woo Han

Chang Kun Park

Jae Min Jang

Kun Woo Park

Seong Hwi Song

Jong Woon Kim

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Semiconductor memory device having pads

The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Domain crossing circuit of a semiconductor memory apparatus

A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.

Phase detection circuit

An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.

Apparatus for transmitting signal in semiconductor integrated circuit

A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.

Data alignment circuit of semiconductor memory apparatus

A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.

Semiconductor apparatus

A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.

Low power, high speed receiver circuit for use in a semiconductor integrated circuit

A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.

DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit

A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Signal receiver circuit capable of improving area and power efficiency in semiconductor integrated circuits

A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

Phase detecting circuit and clock generating apparatus including the same

A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.

Growing community of inventors

Gyeonggi-do, South Korea

Hee Woong Song