Samsung Electronics Co., Ltd.

Nhn Corporation

Ewha University-Industry Collaboration Foundation

Hee-Won Lee

Ju-Yong Kim

Dong-Hun Kwak

Jun-Ho Seo

Hee-Woong Kang

Sang-gu Kang

Jung-Ho Song

Dae-Seok Byeon

Dong-Ku Kang

Ju-Seok Lee

Jin-wook Lee

Mi Young Kim

Kyoung-oh Choi

Yun-Jung Lee

Wook-Ghee Hahn

Ju Seok Lee

Dong-Gi Lee

Joon-Suc Jang

Ji-Su Kim

Mi-Sun Kim

Seong-Jun Ahn

Kyunglim Lee

Suk-Eun Kang

Sang-kwon Moon

Jong-youl Lee

Young-Ha Choi

Jeehye Maeng

Chan-Ha Kim

Se-Jin Chun

Seung-Kyung Ro

Ji-Hun Yoon

Dong Hae Shin

Young-Ran Han

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Nonvolatile memory devices

A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

Nonvolatile memory devices and memory systems

The present invention relates to a receptor-binding domain of an IgE-dependent histamine releasing factor (HRF), and a use thereof, and more specifically, ascertains, as an HRF structural region, and a FL domain and an H2 domain which bind to a receptor of HRF existing in a cell membrane, ascertains the C-terminus domain of the HRF, and ascertains that a material binding thereto inhibits IL-8 secretion, thereby determining that the FL and H2 domains and the C-terminus domain can be utilized in: the development of a therapeutic agent for treatment and prevention of HRF-related disease including allergic diseases such as asthma, bronchitis, chronic obstructive pulmonary disease, bronchiectasis, rhinitis, atopic dermatitis, hives (urticaria), hay fever, conjunctivitis, and anaphylaxis; inflammatory diseases such as bronchitis, pneumonia, arthritis, nephritis, psoriasis, dermatitis, Crohn's disease, enteritis, gingivitis, arteriosclerosis, coronary arteritis, hepatitis, Behcet's disease, bladder cancer, prostatitis, pyelonephritis, glomerulonephritis, osteomyelitis, thyroiditis, uveitis, abdominal cavity inflammation, meningitis, pulmonary fibrosis and rheumatoid arthritis; and malaria, and a method for screening for the HRF-related diseases.

Binding inhibitor between TCTP dimer type IGE-dependent histamine releasing factor and receptor thereof, and use thereof

An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.

Storage device having parameter calibration function, and operating method thereof

Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.

Methods of detecting fast reuse memory blocks and memory block management methods using the same

A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Non-volatile memory device

A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

Systems and methods for performing a program-verify process on a nonvolatile memory by selectively pre-charging bit lines associated with memory cells during the verify operations

A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same

In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.

Non-volatile memory device and method of operation therefor

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Seoul, South Korea

Hee-Won Lee