Samsung Electronics Co., Ltd.

Hee-sung Kang

Chang-bong Oh

Young-Wug Kim

Kyung-soo Kim

Hyuk-ju Ryu

Kyung-Soo Kim

Sang-Jin Lee

Sang-jin Lee

Jun Hui Kim

Young-wug Kim

Chang-Bong Oh

Young-gun Ko

Sung-bae Park

Chang-hyun Park

Eun-Han Kim

In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

A method of fabricating a semiconductor device forms a shallow source/drain region after a deep source/drain region. First, a gate insulating layer including a gate pattern and a gate electrode are formed on a semiconductor substrate. A buffer insulating layer, a first insulating layer, and a second insulating layer are then sequentially formed on the entire surface of the gate pattern and the semiconductor substrate. A first spacer is formed on the first insulating layer at both sidewalls of the gate pattern by etching the second insulating layer. A deep source/drain region is then formed on the semiconductor substrate as aligned by the first spacer. The first spacer is removed. Next, an offset spacer is formed at both sidewalls of the gate pattern by etching the first insulating layer. Finally, a shallow source/drain region is formed on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.

Method of fabricating a semiconductor device having a shallow source/drain region

MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

Methods of fabricating MOS field effect transistors with pocket regions using implant blocking patterns

An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.

SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same

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Seongnam, South Korea

Hee-sung Kang