Samsung Electronics Co., Ltd.

Hee Sung Chae

Kyung Tae Kim

Kyung Min Kim

Kyung-Min Kim

Yun Hwan Jung

Seung Hoon Jung

Hyeok Jong Lee

Hyuk Jun Oh

Woong Joo

Sung Yong Kim

Jin Woo Kim

Kyung-min Kim

Kyoung Min Koh

Sun Jung Kim

Han Soo Lee

Yun Hong Kim

Sun Yool Kang

Dah Som Kim

An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

Image sensor and method of operating an image sensor

An image sensor includes a pixel configured to generate a pixel signal, using an analog signal processing voltage, a ramp signal generator configured to generate a ramp signal, using the analog signal processing voltage, a bias voltage generator configured to generate a bias voltage, using the analog signal processing voltage, and a noise compensator configured to generate a noise component, using a digital signal processing voltage and the analog signal processing voltage, and add the generated noise component to the generated bias voltage. The image sensor further includes a conversion circuit configured to generate a reference voltage, based on the generated ramp signal and the bias voltage to which the noise component is added, and generate an image signal by performing analog-to-digital conversion on the generated pixel signal, based on the generated reference voltage.

Image sensor including noise compensator and image sensing system including the same

A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

Pulse generator of image sensor and method of driving the same

Analog-digital converter and image sensor including thereof

A correlated double sampling (CDS) circuit including a comparator, the comparator including: a signal input unit including a first transistor configured to receive a ramp signal and a second transistor configured to receive a pixel signal; and an offset generator unit connected to the signal input unit, the offset generator unit including at least two transistors, wherein in the offset generator unit, an aspect ratio of the at least two transistors in an auto-zeroing period and an aspect ratio of the at least two transistors in a pixel signal decoding period are different from each other.

Correlated double sampling circuit, an image sensor, and a method for varying output signals in a correlated double sampling circuit

The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Image sensor for distributing output peak current and image processing system including the same

An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n&#x2212;1) delay clock signals to the counters, respectively, 'n' being a natural number equal to or greater than two. Each delay clock signal of the (n&#x2212;1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Image sensor using offset code for counting

Growing community of inventors

Hwaseong-si, South Korea

Hee Sung Chae