Samsung Electronics Co., Ltd.

Hee-Sun Chae

Kyoung-Shin Park

Jeong-Hun Park

Chan-Hoon Park

Sun-Yong Lee

Soo-Woong Lee

Jae-Hyung Jung

Kun-Hyung Lee

Hyun-Ho Cho

Seok-Hyun Kim

Seung-hoon Tong

Jong-Hwan Weon

Kyung-Bo Sim

Hee-Se Kang

Doh-Soon Kwak

Yll-Seug Park

Jae-Seok Oh

Joung-hyun Lim

Tae-Ha Jun

Dae-Sik Cho

Tae-Yang Yoon

A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.

Semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby

An apparatus and method for manufacturing semiconductor devices are disclosed. In accordance with the invention, a wafer transfer device for transferring wafers from wafer storage containers to wafer processing equipment includes a flow chamber designed to reduce the amount of contaminants that can enter the wafer container. The wafer transfer apparatus provide two gas inlets for allowing two gases to flow through the flow chamber of the transfer apparatus. This results in a reduced amount of contaminants able to enter the wafer container, which in turn results in manufacture of devices with more reliable performance characteristics as well as high manufacturing yield.

Apparatus and method for processing wafers

A method for preventing process errors in a semiconductor fabricating process allows only a few authorized engineers to release interlocks of semiconductor fabricating equipment when a count of interlock occurrences exceeds a predetermined number within a predetermined period of time. By allowing a semiconductor fabricating equipment operator only limited ability to reset equipment interlocks, repeated interlock conditions caused by test specification failures may be over-ridden only a predetermined number of times before the semiconductor fabricating equipment is disabled completely. The disabled semiconductor fabricating equipment may only be re-enabled using an authorization code, which is only made available to selected personnel, thereby ensuring that necessary repairs and corrections have been implemented on the semiconductor fabricating equipment.

Process error prevention method in semiconductor fabricating equipment

A lot dispatching method and system for variably applying the most suitable processing equipment and/or processing condition in a succeeding process of a semiconductor manufacturing process, wherein the succeeding process is influenced by the result of a preceding process. A lot processed by the preceding process is dispatched to the succeeding processing equipment according to a systematic analysis result obtained from a relationship between a process result of the preceding process and an efficiency and the characteristics of a plurality of processing equipment in the succeeding process. A plurality of process conditions for the succeeding process corresponding to the performance of the preceding process is provided. A respective process condition has characteristics that minimize the difference in performance in the succeeding process from a desired or target performance. By systematically analyzing the quality of the lot waiting to be dispatched, the succeeding process is performed with the most suitable process condition.

Lots dispatching method for variably arranging processing equipment and/or processing conditions in a succeeding process according to the results of a preceding process and apparatus for the same

A lithography system includes a spinner, a first controller, a stepper and a second controller. The spinner coats a photoresist film on a semiconductor substrate. The first controller sets a first optimal process parameter according to external information regarding the semiconductor wafer and controls the spinner according to the first optimal process parameter, when the semiconductor wafer is loaded into the spinner. The stepper exposes the semiconductor wafer, which is coated with the photoresist film, to light of a predetermined wavelength. The second controller sets a second optimal process parameter according to the external information regarding the semiconductor wafer and controls the stepper according to the second optimal process parameter, when the semiconductor wafer coated with the photoresist film is loaded into the stepper.

Lithography system including mechanism for setting optimal process parameters and method of operating the same

A dry etching apparatus is capable of suppressing formation of reaction products (i.e., polymers) in an etching chamber. A gas supply is connected to the top of the etching chamber by a first gas duct, and a pump is connected to the bottom of the etching chamber by a second gas duct. An upper electrode is furnished in the etching chamber. At a location opposed to the upper electrode, a lower electrode is furnished. Insulation plates of the upper and the lower electrodes, or an insulation plate of either of the upper or the lower electrode, include a plurality of grooves. The etching chamber may include a plurality of grooves and projections on its sidewalls. The plurality of projections in the sidewalls has a semicircular or a rectangular cross-section, and may be formed as a single body or as individually detachable projection bodies. Accordingly, it is possible to improve the conductance and exhaustion velocity in the etching chamber using the plurality of grooves in the insulation plates of the electrodes and the grooves in the sidewalls of the chamber. As a result, the formation of polymers that may act as particles during an etching process can be suppressed. Additionally, the accumulated polymers can be more widely dispersed.

Dry etching apparatus having upper and lower electrodes with grooved

Growing community of inventors

Gyeonggi-do, South Korea

Hee-Sun Chae