Samsung Electronics Co., Ltd.

Hee-seok Eun

Jun-Jin Kong

Yong-June Kim

Han-woong Yoo

Jaehong Kim

Jae-Hong Kim

Sang-Hoon Lee

Seung-Hwan Song

Dong-Hyuk Chae

Hong-Rak Son

Young-Hwan Lee

Kyoung-Lae Cho

Ki-Jun Lee

Jong-han Kim

Sun-Mi Yoo

Jae-hong Kim

Jong-youl Lee

Seok-min Yoon

A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose voltage levels are different from a voltage level of the first hard read voltage, while the flash memory performs a first operation on the hard data.

Flash memory and reading method of flash memory

An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Interleaving apparatuses and memory controllers having the same

A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed.

Flash memory device, memory system and method of operating the same

The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nbits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nbits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nbits of the data are completely programmed or read, programs or reads an (N+1)bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nbits of the data, to program or read for 2cell distributions of 2cell distributions corresponding to the (N+1)bit of the data and then programs or reads for other 2cell distributions.

Flash memory device, programming and reading methods performed in the same

Growing community of inventors

Hwaseong-si, South Korea

Hee-seok Eun