Samsung Electronics Co., Ltd.

Hee-Seog Jeon

Jeong-Uk Han

Seung-Beom Yoon

Yong-Tae Kim

Bo-Young Seo

Yong-kyu Lee

Hyun-Khe Yoo

Sung-Taeg Kang

Myung-Jo Chun

Ji-Do Ryu

Young-Ho Kim

Yong-Kyu Lee

Jung-Ho Moon

Bo-young Seo

Hyok-Ki Kwon

Sung-Gon Choi

Yong-Suk Choi

Chang-Min Jeon

Chang-Hun Lee

Seung-Jin Yang

Kwang-Tae Kim

Kwang-Wook Koh

Jae-Hwang Kim

Soung-Youb Ha

Tae-kwang Yu

Tea-Kwang Yu

Ji-Hoon Park

Kee-Moon Chun

Choong-jae Lee

Choong-Jae Lee

Chang-Min Jeong

A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Magnetic memory devices including magnetic memory cells having opposite magnetization directions

A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Magnetic memory devices including shared lines

A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Split-gate type nonvolatile memory device, semiconductor device having split-type nonvolatile memory device embedded therein, and methods of forming the same

A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.

Semiconductor devices having asymmetric doped regions and methods of fabricating the same

A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.

Non-volatile memory device, system, and cell array

A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

High voltage transistor

A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same

A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Non-volatile memory device

A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device

In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same

A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

Non-volatile memory integrated circuit device and method of fabricating the same

In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Methods of forming nonvolatile memory devices

There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

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Suwon-si, South Korea

Hee-Seog Jeon