Samsung Electronics Co., Ltd.

Hee-Mun Bang

Heung-bae Lee

Yun-seong Eo

Kwang-du Lee

Sung-jae Jung

Sang-yoon Jeon

Heung-Bae Lee

Seong-soo Lee

Tae-Wook Kim

Kyoung-Jin Lee

Ick-jin Kwon

Je-Hyung Yoon

Dae-ki Kim

Hyoung-Seok Oh

Andrew Han

Chong-ouk Kim

In a clock-based soft-start circuit configured to generate a soft-start reference voltage that restrains an inrush current at an initialization of power supplied to a DC-DC converter, the clock-based soft-start circuit comprises a time setting unit configured to set a soft-start time period in response to a clock signal. A ramp circuit is configured to generate a soft-start reference voltage which is ramped upward or downward between a base level and a reference voltage level during the soft start time period set by the time setting unit. In this manner, the clock-based soft-start circuit is applicable for all DC-DC converters and the soft-start in a linear slope is possible.

Clock-based soft-start circuit and power management integrated circuit device

A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.

Digital phase detector, and digital phase locked loop including the same

A radio frequency identification (RFID) reader is provided, having a transmitting circuit that generates a transmitted signal to operate an RFID tag, a receiving circuit that receives a received signal including a tag signal from the RFID tag and a transmission carrier leakage signal leaking from the transmitting circuit, and a leakage removing circuit that senses a phase and amplitude of the transmission carrier leakage signal inputted to the receiving circuit, converts the transmitted signal from the transmitting circuit into a signal having a phase opposite to that of the transmission carrier leakage signal and an amplitude equal to that of the transmission carrier leakage signal, and synthesizes the converted signal and the received signal inputted to the receiving circuit.

RFID reader and method for removing a transmission carrier leakage signal

An inductor circuit includes a pair of inductors connected in parallel with each other and a switch for turning on and off electric power to one of the pair of inductors. The inductance of the inductor circuit can be varied and the quality factor Q can be improved. Further, RF circuits employing the inductor circuit can generate an intended operating frequency.

Parallel-structured switched variable inductor circuit

An N&#xd7;N multiple-input multiple-output (MIMO) transceiver is provided. The transceiver includes a plurality of transceivers, each including at least one transceiver circuit; an oscillation unit which is configured to generate a differential signal which is supplied to the at least one transceiver circuit; a plurality of buffers, which are mounted in a bypass line between the at least one transceiver circuit and the oscillation unit and are configured to amplify and bypass the differential signal or input and amplify the differential signal; and a buffer control unit which is configured to control the plurality of buffers to bypass or input the differential signal.

NxN multiple-input multiple-output transceiver

An integrated circuit having integrated inductors includes at least one pair of transistors, and at least one inductor group which includes a pair of inductors coupled to the at least one pair of the transistor, respectively. The pair of the inductors form a spiral shape on a plane and the inductors arranged symmetrically to each other. Magnetic fluxes, which are generated by current flows along the inductors of the at least one inductor group, are formed in a direction to mutually intensify the magnetic fluxes according to differential signals applied to the at least one transistors from outside. Accordingly, high inductance and high quality factor can be attained owing to the positive magnetic coupling of the inductors.

Integrated circuit having integrated inductors

A sigma-delta modulation method with low complexity is provided. To this end, in the present invention, an input signal is forwarded and an output signal is fed back to thus reduce the range of the noise transfer function of the sigma-delta modulator and to lower the frequency offset and the phase noise at low frequencies. A sigma-delta modulator for a frequency synthesizer may include one or more modulation units which are connected in series and perform a sigma-delta modulation to an input signal and a provided accumulated signal using a signal which is weighted with a feedback coefficient; and an output adder which adds an output signal from a terminal section of the modulation units and the input signal, and outputs the added signal for feedback to the modulation units.

Apparatus and method of stabilizing sigma-delta modulator for fractional-N phase-locked-loop

A method and a system for calibrating an input voltage of a voltage controlled oscillator and a digital interface used for calibrating the input voltage. The method includes: setting a lock detection time for tuning a signal phase; setting a lock detection voltage section; setting output frequency values at predetermine spacings; checking connection states of capacitors of the capacitor bank necessary for a lock of the output frequency values; storing information regarding the connection states of the capacitors in the output frequency values; and if one of the output frequency values is determined depending on a change of a channel, setting connection states of the capacitors according to the information regarding the connection state corresponding to the one frequency value. The capacitor bank includes: a predetermined number of capacitors having different capacitances and connected to one another in parallel; and switches connected to the capacitors in series.

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Seoul, South Korea

Hee-Mun Bang