Samsung Electro-mechanics Co., Ltd.

Hee Kon Lee

Seung Wook Park

Young Do Kweon

Jin Gu Kim

Hyung Jin Jeon

Jong Yun Lee

Ju Pyo Hong

Young Ho Kim

Mi Jin Park

Seon Hee Moon

Jing Li Yuan

Yuan Jing Li

Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.

Interposer-embedded printed circuit board

The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Stacked wafer level package and method of manufacturing the same

A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Method of manufacturing stacked wafer level package

The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

Method of manufacturing wafer level package including coating and removing resin over the dicing lines

Growing community of inventors

Hwaseong-si, South Korea

Hee Kon Lee