Samsung Electronics Co., Ltd.

Hee-jun Shim

Yen-Jo Han

Yeon-Gon Cho

Jin-Sae Jung

Jae-Young Kim

Young-chul Cho

Soo-Jung Ryu

Woong Seo

Dong-Hoon Yoo

Ho-Young Kim

Jin-Seok Lee

Seong-Hoon Jeong

Min-Wook Ahn

Moo-Kyoung Chung

Chang-Moo Kim

Jin-sae Jung

Sun-min Kwon

Provided are a texture compressing method and a texture compressing apparatus, which compress some color information of a texture block, which is unable to realize all colors included in the texture block by a determined compression bit number, to be stored in a compression data bit of a texture block, which is able to realize all colors included in the texture block by a bit number lower than the determined compression bit number, based on a color distribution of each texture block, and a texture decompressing method and a texture decompressing apparatus corresponding to the texture compressing method and the texture compressing apparatus.

Texture compressing method and apparatus and texture decompressing method and apparatus

An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Apparatus and method for generating test cases for processor verification, and verification device

Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.

Hardware debugging apparatus and method for software pipelined program

Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion

An apparatus for detecting a source code error location in a mixed-mode program is disclosed. The apparatus may include a compiler, a mapping table generator, a simulator, a comparison data generator and an error location detector. The apparatus extracts low-level data while simulating a verification program and while simulating a reference program. The low-level data is mapped to mapping tables for a verification program and a reference program, and by comparing the tables it is determined if there is an error in the mixed-mode program and if so, where.

Apparatus and method for detecting location of source code error in mixed-mode program

An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

Apparatus and method for compressing trace data

An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.

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Seoul, South Korea

Hee-jun Shim