Qualcomm Incorporated

Microsoft Technology Licensing, LLC

Hee Jun Park

Mehmet Iyigun

Abhinav Goel

Shay Landis

Robert Allen Shearer

Parag Arun Agashe

Young Hoon Kang

Ronald Alton

Richard Gerard Hofmann

Jon James Anderson

Bohuslav Rychlik

Rajat Mittal

Sravan Kumar Ambapuram

Shirish Kumar Agarwal

Soumya Das

Mehdi Saeidi

Christopher Kong Yee Chun

Meir Tzur

James Francis Geekie

Eran Pinhasov

Joshua Stubbs

Tauseef Kazi

Andrew James Frantz

Christopher L Medrano

Yong Ju Lee

Ron Gaizman

Sean Sweeney

Huang Huang

Alex Tu

Wilson Kwan

Sudeesh Reddy Pingili

Mohammad Tamjidi

Travis Scott Legg

Krishna V S S S R Vanka

Eric Charles Abbott

Inho Hwang

Sumant Madhav Paranjpe

Yiran Li

Colin Beaton Verrilli

Babak Forutanpour

Dexter Tamio Chun

Sivaramakrishna Veerepalli

Peng Wang

David Yunusov

Shadi Hawawini

Moshe Ben-Ari

Steven S Thomson

Haw-Jing Lo

Arpit Mittal

Jewon Kang

Shih-Hsin Jason Hu

Sean Vincent Maschue

Alex Kuang-Hsuan Tu

R Nicholson Gibson

Yuancheng Christopher Pan

Taewoo Kwak

Krishna Vsssr Vanka

Tao Xue

Cristian Duroiu

Ted E Williams

Mriganka Mondal

Robert Nicholson Gibson

VaraPrasad Arikatla

Juhi Saha

Thomas Andrew Morison

Keunsoo Roh

Christoper Lee Medrano

Niraj Shantilal Paliwal

Victorya Vishnyakov

Ashvinkumar Namjoshi

Harshad Bhutada

Viswanathan Kumaragurubaran

Christopher Kong Chun

Andrew J Frantz

Christopher Lee Medrano

Ronald Frank Alton

Joshua Hirsch Stubbs

Vara Prasad Arikatla

A method for an artificial neural network includes receiving a set of input values to be convolved with multiple kernels via multiple computing units. One or more thermally-stressed computing units of the multiple computing units are determined. The multiple kernels are mapped to the multiple computing units of a system-on-chip (SOC) based on the one or more thermally-stressed computing units. A convolution is performed on the set of input values and a most sparse kernel of the multiple kernels on the most thermally-stressed computing unit.

Sparsity-based neural network mapping to computing units in a system-on-chip

Systems and techniques are provided for vision perception processing. An example method can include determining an attention demand score or characteristic per region of a frame from a sequence of frames; generating attention votes per region of the frame based on the attention demand score or characteristic per region, the attention votes per region providing attention demands and/or attention requests; determining an attention score or characteristic per region of the frame based on a number of attention votes from one or more computer vision functions; based on the attention score or characteristic per region of the frame, selecting one or more regions of the frame for processing using a neural network; and detecting or tracking one or more objects in the one or more regions of the frame based on processing of the one or more regions using the neural network.

Efficient vision perception

Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.

Allocation of data sub-tensors onto hardware sub-arrays

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

Performance scaling for binary translation

Certain aspects of the present disclosure provide a method for performing parallel data processing, including: receiving data for parallel processing from a data processing requestor; generating a plurality of data sub-blocks; determining a plurality of data portions in each data sub-block of the plurality of data sub-blocks; changing an order of the plurality of data portions in at least one data sub-block of the plurality of data sub-blocks; providing the plurality of data sub-blocks, including the at least one data sub-block comprising the changed order of the plurality of data portions, to a plurality of processing units for parallel processing; and receiving processed data associated with the plurality of data sub-blocks from the plurality of processing units.

Processing data stream modification to reduce power effects during parallel processing

Embodiments include methods performed by a processor of a vehicle for allocating processing resources to concurrently-executing neural networks. The methods may include determining a priority of each of a plurality of neural networks executing on a vehicle processing system based on a contribution of each neural network to overall vehicle safety performance, and allocating computing resources to the plurality of neural networks based on the determined priority of each neural network. In some embodiments, the methods may dynamically adjust hyperparameters of one or more neural networks.

Allocating processing resources to concurrently-executing neural networks

In a real-time system having first and second processor systems, cooperative dynamic clock and voltage scaling ('DCVS') may include a first processor system monitoring a condition indicative of first processor workload, adjusting a first processor operating frequency in response to a detected amount of change in the first processor workload, and providing an indication based on the detected amount of change in the first processor workload to the second processor contemporaneously with providing first processor output data to the second processor. The cooperative DCVS may further include the second processor system adjusting a second processor operating frequency in response to the indication.

Cooperative dynamic clock and voltage scaling (DCVS) between two processor systems

Neural network workload re-allocation in a system-on-chip having multiple heterogenous processors executing one or more neural network units may be based on measurements associated with the processors' conditions and on metadata associated with the neural network units. Metadata may be contained in an input file along with neural network information. Measurements characterizing operation of the processors may be obtained and compared with one or more thresholds. A neural network unit executing on a processor may be identified as a candidate for re-allocation based on metadata associated with the neural network unit and results of the comparisons. A target processor may be identified based on the metadata and results of the comparisons, and the candidate neural network neural network unit may be re-allocated to the target processor.

Run-time neural network re-allocation across heterogeneous processors

Systems and methods may include indicating a processing latency requirement to an operating frequency controller of a moving device processing system, receiving an indication of the allowable operating frequency for the processing system, and changing a characteristic of movement of the moving device based on the allowable operating frequency indication. Some embodiments include receiving an indication of a processing latency requirement from a moving device control system, determining a target operating frequency to achieve the processing latency requirement, determining whether the target operating frequency exceeds an allowable operating frequency, and indicating the allowable operating frequency for the processing system to the moving device control system. Further embodiments include receiving an indication of a speed of the moving device, determining a target operating frequency for the processing system compatible with the indicated speed of the moving device, and changing an operating frequency of the processing system to the target operating frequency.

Interactive control of moving device speed and processing system operating frequency

Techniques described herein provide for filtering and prioritizing incoming messages, which can help reduce and smooth out the processing load on components used to process the incoming messages. Filtering techniques may comprise identifying a subset of nearby vehicles from which messages are to be processed, and further calculating remaining delay budgets with regard to the messages to prioritize them for processing. Different techniques for determining a subset of nearby vehicles can be used, and/or remaining delay budgets may be calculated and/or communicated in different ways.

C-V2X message processing timeline adaption based on contouring of remote vehicles and available delay budget

Techniques and systems are provided for machine-learning based image stabilization. In some examples, a system obtains a sequence of frames captured by an image capture device during a period of time, and collects motion sensor measurements calculated by a motion sensor associated with the image capture device based on movement of the image capture device during the period of time. The system generates, using a deep learning network and the motion sensor measurements, parameters for counteracting motions in one or more frames in the sequence of frames, the motions resulting from the movement of the image capture device during the period of time. The system then adjusts the one or more frames in the sequence of frames according to the parameters to generate one or more adjusted frames having a reduction in at least some of the motions in the one or more frames.

Image stabilization using machine learning

Embodiments include methods for managing the processing of data and performing computing tasks of a wireless device using computing resources of a remote network computing device. A wireless device and a network computing device may dynamically track factors affecting a round-trip latency of a computing task. The wireless device and the network computing device may generate and send metadata including the factors and a latency budget for the computing task. The wireless device and the network computing device may adjust a processing time for processing data related to the computing task based the received metadata and the latency budget.

Processing data using remote network computing resources

User equipment (UE) may benefit from power management techniques, for example, in the context of cellular vehicle-to-everything (CV2X) communication. In various aspects of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE configured to determine whether a first subframe includes at least one sub-channel carrying information intended for the UE, receive the information via at least one receive (Rx) chain associated with the at least one sub-channel when the information intended for the UE is carried on the at least one sub-channel included in the first subframe, and deactivate the at least one Rx chain associated with the at least one sub-channel based on whether the information intended for the UE is absent from the at least one sub-channel included in the first subframe.

System and method for power management based on subframe content

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San Diego, CA, United States of America

Hee Jun Park