Skhynix Inc.

Dialog Semiconductor Korea Inc.

Industrial Cooperation Foundation Chonbuk National University

Hee Jun Kim

Minsoon Hwang

Jung Hwan Lee

Chan Keun Kwon

In Seok Kong

Beomjin Kim

Sung Ah Lee

Jae Hyeong Hong

Jun Seo Jang

Sang Won Lee

Hang Geun Jeong

Eun Suk Park

A calibration device is coupled to a communication line shared by plural devices. The calibration device is configured to perform an iterative eye width scanning by adjusting a set voltage level by a preset level from a first voltage level to a reference center voltage level, wherein the first voltage level corresponds to a cross point where values of signals or data, which are transmitted via the communication lines, are changed in different directions; and determine, as a zero crossing for the signals or the data, a voltage level corresponding to a largest value among a plurality of eye widths obtained through the iterative eye width scanning.

Calibration device and memory device including the calibration device for a high-speed data I/O operation under a low power condition

A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

Reference voltage training circuit and semiconductor apparatus including the same

A pulse counting apparatus operating at a low power and an operation method thereof are provided. The pulse counting apparatus includes a pulse counter configured to count a number of pulses inputted from outside of the pulse counting apparatus and generate an interrupt signal; a timer unit configured to generate a wake-up signal according to a preset time; a real time clock (RTC) configured to serve as a clock of the pulse counter and the timer unit; and a processor configured to switch from a sleep mode to an active mode when the interrupt signal or the wake-up signal is generated.

Pulse counting apparatus operating at low power and operation method thereof

A sensor data transmitting apparatus that transmits sensor data with low power and a method therefor are provided. According to an embodiment of the disclosure, a sensor data transmitting apparatus that transmits sensor data includes: a wireless communicator configured to access a network through an access point (AP); a timer module configured to generate a wake-up signal in a predetermined cycle; a storage configured to include a non-volatile memory and a volatile memory, a small booting code and a full booting code being recorded in the non-volatile memory and the volatile memory being capable of recording the sensor data; and a processor configured to execute the small booting code or the full booting code, collect the sensor data from a sensor after executing the small booting code, and transmit the sensor data to the AP.

Method and apparatus for transmitting sensor data with low power

A launch device for launching an electronic apparatus comprises a storage unit, a main storage and a processor. The storage unit is configured to store a mini-launch code for executing a detection of an output value of a sensor, and store system driving codes which comprises a standard launch code for launching electronic apparatus. The main storage loads the mini-launch code and the system driving codes. The processor loads and executes the mini-launch code or the standard launch code.

Launch device for electronic apparatus and method thereof

A data output circuit includes: a voltage generation circuit configured to generate an operating voltage having a potential level higher than levels of a first power supply voltage and a second power supply voltage; a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to calibration code signals and the operating voltage; a data pre-driver circuit configured to generate and output internal data according to a data signal and the first power supply voltage; and a main driver circuit configured to generate output data according to the internal data and the second power supply voltage, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.

Data output circuit

A memory system includes: a buffer memory device; and a memory controller configured to communicate data with the buffer memory device, wherein the memory controller includes: an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage; and an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal.

Memory system having impedance calibration circuit

A memory system includes: a buffer memory device including a reference voltage pad; a memory controller including a controller ZQ pad; and a controller calibration resistor, wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other.

A memory system includes: a buffer memory device; and a memory controller including a data output driver configured to output data to the buffer memory device, wherein the data output driver includes: a pull-up switching unit coupled to an input/output power voltage, the pull-up switching unit including a PMOS transistor controlled by a data signal that varies according to the output data; a pull-up resistor unit including an NMOS transistor coupled to a DQ pad; a pull-down switching unit controlled by the data signal; and a pull-down resistor unit coupled to the pull-down switching unit.

Memory system

A circuit for controlling a collector current of a substrate bipolar junction transistor (BJT) is provided. The circuit includes a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT, a current transmitter configured to transmit the first mirroring base current, a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT, and a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

Control circuits of collector current of substrate bipolar junction transistors and circuits of compensating for base current for generating a proportional to absolute temperature (PTAT) voltage using the control circuits

Growing community of inventors

Gyeonggi-do, South Korea

Hee Jun Kim