Samsung Electronics Co., Ltd.

Hee-Joong Oh

Hyung-Dong Kim

Jae-Hoon Joo

Tae-Sik Son

Byung-heon Kwak

Na-Rae Kim

Young-Min Jang

In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

Growing community of inventors

Hwaseong-si, South Korea

Hee-Joong Oh