Samsung Electronics Co., Ltd.

Hee-jin Lee

Joong-Hyun Baek

Dae-ho Lee

Seok-hong Kwon

Sun-Won Kang

Bu-won Kim

Sang-nam Jeong

Jin-Kwon Bae

Woo-Dong Lee

Hyo-Soon Kang

Tae-Young Yoon

A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.

Semiconductor package having a circuit pattern

A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.

A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.

Semiconductor package

A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

Stack semiconductor package

A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Multi-chip package and method of manufacturing the same

Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Method of manufacturing semiconductor package

A light emitting device with improved heat dissipation is provided. The light emitting device includes a first lead frame, a second lead frame, a light emitting element and a housing. The first lead frame includes a light emitting element mounting portion, a first heat dissipation portion extending from the light emitting element mounting portion in a first direction, and second and third heat dissipation portions extending from the light emitting element mounting portion in a second direction opposite to the first direction. The second lead frame extends in the second direction and is disposed between and spaced apart from the second and third heat dissipation portions. The light emitting element is mounted on the light emitting element mounting portion and is electrically coupled to the first and second lead frames. The housing encapsulates the first and second lead frames. The second and third heat dissipation portions have a first width and the second lead frame has a second width the same as or different from the first width.

Light emitting device

A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Wafer stacked package waving bertical heat emission path and method of fabricating the same

A semiconductor module includes a semiconductor package generating thermal energy, a heat collecting member transferring thermal energy from the semiconductor package to a heat collection area in the heat collecting member, a heat radiating member transferring thermal energy received from the heat collecting member and package to the outside, and a thermoelectric device transferring thermal energy through the heat collection area to the heat radiating member via the thermoelectric effect. The heat collecting member and heat radiating member may be otherwise insulated so thermal energy is transferred and controlled by the thermoelectric device. The package may be a dynamic random access memory (DRAM), microprocessor, central processing unit (CPU), graphic processing unit (GPU), or flash memory. The heat radiating member may be an external case of a solid state disk (SSD), and the thermoelectric device may be a Peltier cooler controlled through a power line.

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Seongnam-si, South Korea

Hee-jin Lee