Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Hee-Jin Ahn

Bernhard Egger

Tai-song Jin

Won-Sub Kim

Dong-Hoon Yoo

Jin-Seok Lee

Min-Wook Ahn

Sun-hwa Kim

Yeon-Gon Cho

Sung-Joo Yoo

Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Reconfigurable processor using power gating, compiler and compiling method thereof

An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

NOP instruction compressing apparatus and method in a VLIW machine

A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Apparatus and method for reducing overhead caused by communication between clusters

Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Reconfigurable processor and method for processing loop having memory dependency

A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Reconfigurable processor and method for processing a nested loop

An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Apparatus and method for dynamically determining execution mode of reconfigurable array

A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Growing community of inventors

Seoul, South Korea

Hee-Jin Ahn