Hynix Semiconductor Inc.

Hee Jeong Son

Nak Heon Choi

Kook Whee Kwak

Jung Eon Moon

Si Woo Lee

Joon Won Lee

Dae Gwan Kang

Seong Hoon Jeong

Suk Yun

Yun Suk

The present invention describes an electrostatic discharge protection circuit that protects an internal circuit of a semiconductor device from electrostatic discharge. The electrostatic discharge protection circuit includes a first electrostatic protection unit that transfers static electricity as a driving signal and also discharges the static electricity to a first discharge line when the static electricity is generated in a pad. It also includes a second electrostatic protection unit that discharges the static electricity generated in the pad to a second discharge line in response to the driving signal transferred from the first electrostatic protection unit. Since the first electrostatic protection unit performs an electrostatic discharge operation and at the same time aids the driving of the second electrostatic protection unit, electrostatic discharge performance can be enhanced while a layout area of the electrostatic discharge protection circuit can be reduced.

Electrostatic discharge protection circuit having a reduced size and enhanced discharge

An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

Electrostatic discharge protection circuit and electrostatic discharge protection method of a semiconductor memory device

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Seoul, South Korea

Hee Jeong Son