Goldstar Electron Co., Ltd.

Hee G Lee

Young Kwon Jun

Seong J Jang

Kwang H Yun

A dynamic random access memory having an improved layout capable of having a large storage capacity with a small memory cell area as well as preventing the occurrence of short-circuiting by an increase in the process margin, and a method of arranging memory cells of the same. Each active region includes a first diffusion region, a second diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second diffusion regions. First diffusion regions of adjacent active regions are located at positions symmetrical with respect to the common second diffusion region, at a predetermined angle. Each of uniformly spaced bit lines has a protrusion having a predetermined width and length and extending from its one edge in a direction that the word lines extend. At the protrusion, one second diffusion region is disposed. Uniformly spaced word lines cross bit lines. Each capacitor is positioned between two adjacent bit lines and between two adjacent word lines. Each first contact hole is located on the center of each capacitor. Each bit line has a bent portion for preventing a short-circuiting caused by a contact with a protrusion of adjacent bit line. Each word line has a bent portion for preventing a short-circuiting caused by a contact with each corresponding first contact hole.

Dynamic random access memory having improved layout and method of

Dynamic random access memory having improved layout

A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.

Method of making integrated circuit package containing inner leads with

A method of making a semiconductor memory device wherein a storage node having a plurality of pillars, capable of increasing the storage node surface area and thus the cell capacitance. The storage node is formed by depositing a storage node polysilicon film to have a thickness of 5,000 .ANG. to 6,000 .ANG. over a semiconductor substrate, forming a photoresist pattern over the polysilicon film in a direct electron beam writing manner, and etching the polysilicon film up to a depth of 1,000 .ANG. from the upper surfaces of a gate and a bit line by using the photoresist pattern. The formed storage node has a plurality of uniformly spaced pillars. Alternatively, the storage node is formed by forming a smoothing insulating film over the semiconductor substrate depositing a storage node polysilicon film over the smoothing insulating film, primarily photo exposing the semiconductor substrate using a glass mask having phase shifters, secondarily photo exposing the semiconductor substrate under the condition of rotating 90.degree. the semiconductor substrate, to form a check-board photoresist pattern, and patterning the polysilicon film using the photoresist pattern as a mask. The formed storage node has a plurality of pillars arranged independently or intersectionally.

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Seoul, South Korea

Hee G Lee