Samsung Electronics Co., Ltd.

Samsung Semiconductors & Telecommunications Co., Ltd.

Hee-Choul Park

Kook-Hwan Kwon

Su-Chul Kim

Byeong-Yun Kim

Kook-hwan Kwon

Du-Eung Kim

Chang-Rae Kim

Chul-Min Jung

Jong-young Kim

Eun-Cheol Kim

Seung-Kweon Yang

Eun-cheol Kim

Kyeong-Rae Kim

Yong-Bo Park

Hyang-ja Yang

Tae-Gyoung Kang

Hyung-Kyu Lim

Seong-Jin Han

Choong-Keun Kwark

A semiconductor device comprises a plurality of input/output pads, and a plurality of input buffers for receiving external signals synchronized with a clock signal through corresponding ones of the input/output pads, wherein the input buffers are arranged adjacent to each other to minimize skewing of the clock signal to the input buffers.

Semiconductor device having input buffers

Disclosed herein is a semiconductor memory device which comprises a decoding block, an OR gate and first and second precharge circuits. The decoding block generates section word line select signals and column select signals in response to a block select signal and row and column pre-decoder signals. And, the OR gate mixes the section word line select signals to generate a precharge signal. This forces the first precharge circuit to be activated or inactivated in synchronization with the section word line select signals. Furthermore, the second precharge circuit is activated or inactivated in synchronization with the column select signals. According to the precharge scheme of the present invention, there is prevented the period of the inactivation (activation) of the top and bottom precharge signals from being overlapped with the period of the activation (inactivation) of the section word line. As a result, the semiconductor memory device has an improved access speed.

Semiconductor memory with auto-tracking bit line precharge scheme

A synchronous burst semiconductor memory device with a pipelined multi-bit prefetch architecture includes separate internal address generators for respective read and write burst modes. The synchronous memory device also adopts an auto-tracking bit line scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, and strobe clocks synchronized with the output data to guarantee processor data-validation time.

Synchronous burst semiconductor memory device

A burst SRAM device is provided having a burst column selection circuit which is activated in accordance with a burst address, in addition to a column selection circuit for selecting columns of a memory cell array capable of storing a binary data. An internal column address portion of an external column address is applied to the column selection circuit as a first burst address signal. The column selection circuit selects at the same time at least two columns in response to the first burst address signal. During a burst read mode, at least two columns are simultaneously selected in response to the first burst address signal, and data stored in the selected cells are simultaneously sensed and amplified by at least two sense amplifiers corresponding to the selected memory cells. The data amplified thus are stored in a data output register. The burst addresses are applied to the burst column selection circuit. The burst column selection circuit allows the data stored in the data output register to be sequentially delivered to input/output data line pair in response to the burst addresses. As a result, an interval between a generation time of the first burst address and the time, which takes for a sensing operation of the last 1-bit data to be completed by the last burst address, can be considerably shortened as compared with the conventional device. During a burst write mode, at least two columns are simultaneously selected by the first burst address, and 1-bit data from the input/output data line pair corresponding to locations of the first burst address of the data input register are stored. The burst column selection circuit allows the data delivered sequentially from the data line pair to be sequentially stored in regions of the other burst addresses of the data input register in response to the other burst addresses. At least 2-bit data stored in the data input register are sequentially or simultaneously written in the selected memory cells of the selected columns.

Random access memory having burst mode capability and method for

A synchronous semiconductor device being operated in synchronism with an external clock signal includes an internal clock controller and an internal clock generator. The internal clock controller is responsive to an externally applied signal indicative of a beginning of an operation and generates an internal control signal in synchronism with the external clock signal. The internal control signal is only activated for a predetermined time interval long enough to carry out the operation. The internal clock generator serves to generate an internal clock signal synchronized with the external clock signal while the internal control signal is activated. An internal buffer circuit is operated in synchronism with the internal clock signal. Accordingly, power consumption can be reduced while in a standby mode.

Internal clock generation circuit for synchronous semiconductor device

A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse. A third large transistor is connected between the lines of the line pair to equalize the voltages of the lines when the precharge pulse is generated.

Precharge system for a semiconductor memory device

A high-speed data output related circuit for a memory device reduces the operational cycle time by self-latching data in a data output buffer and self-resetting a main sense amplifier and level shifter, thereby the need for external control signals. A data output related circuit in accordance with the present invention includes: a sense amplifier for generating sensed data; a level shifter for converting the level of the sensed data, thereby generating level shifted data; a data output buffer for self-latching the level shifted data in first latch nodes in response to the level shifted data, for latching the level shifted data latched in the first latch nodes in second latch nodes when a data passing clock is received, and for transmitting data latched in the second latch nodes through output terminals in response to an output enable signal; and a controller for sequentially activating, before the level shifted data arc generated, the operations of the sense amplifier and the level shifter by generating a main sensing enable signal and a shifting enable signal as first and second logic levels in response to a sensing enable signal supplied from the device, and for sequentially disabling, immediately after the level shifted data are self-latched, the operations of the sense amplifier and the level shifter by generating the main sensing enable signal and the shifting enable signal as second and first logic levels, thereby causing the data output buffer to be self-reset when the level shifted data are latched in the first latch nodes.

Data output related circuit which is suitable for semiconductor memory

A redundancy decoding circuit for a semiconductor memory device is shown which includes a comparator which decodes and outputs a redundant memory cell address in response to an address signal, where the comparator includes internal fuses that are coupled to an output terminal of the comparator and which can be selectively cut in order to determine the redundant memory cell address. The redundancy decoding circuit also includes a driving unit which supplies a driving current to the output terminal of the comparator in response to a switching control signal. A pulse generator generates a power up pulse having a predetermined width responsive to power up of the redundancy decoding circuit. A switching control signal generator, which includes a master fuse connected in series with a switching element, generates the switching control signal at a predetermined voltage level in response to the power up pulse generated by the pulse generator even when the master fuse is incompletely cut.

Redundancy decoding circuit for a semiconductor memory device

Methods and apparatus are disclosed for receiving and decoding address information applied to a synchronous semiconductor memory device. Separate read address and write address decoders and latches are provided for decoding the address without waiting for a determination as to whether a read cycle or a write cycle is undertaken, thereby reducing the decoding delay and thereby increasing the speed of such a device in operation.

Address decoding . . . semiconductor memory

A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors. In another alternative embodiment, the push-pull buffer includes a PMOS push transistor and an NMOS pull transistor. An inverter, which is powered by the same power supply as the push-pull buffer, drives the gate of the PMOS transistor. Two discharge transistors are connected to the gates of the push-pull transistors, and the gates of the two discharge transistors are cross-coupled to the gate of the NMOS pull transistor and the input of the inverter to assure that at least one of the push-pull transistors are turned off.

Data output buffer for multiple power supplies

An electrostatic discharge structure of a semiconductor device is provided. The structure includes a semiconductor substrate doped with P-type impurities; an N-type well formed in a predetermined region of the semiconductor substrate; a P-type pocket well formed in a predetermined region of the N-type well; an N-type active guardline formed in the surface of the N-type well and doped to a concentration higher than that of the N-type well; a P-type active guardline formed in the surface of the P-type pocket well and doped to a concentration higher than that of the P-type pocket well; and an NMOS transistor formed in a surface of the P-type pocket well. Accordingly, even though a negative voltage due to electrostatic charge is temporarily applied to the drain region of the NMOS transistor, a malfunction of an internal circuitry formed in a P-type semiconductor substrate can be prevented.

Electrostatic discharge structure of semiconductor device

A burn-in test circuit for a semiconductor memory device tests for defective memory cells. The test circuit applies a test signal that turns 'off' transistors in a precharge circuit and applies a select signal to memory cells at predetermined intervals. The select signal and test signal are delayed for different time intervals depending on whether the memory device is transitioning from a normal operating mode to a test mode or from the test mode to the normal operating mode. The selective delay prevents overcurrent conditions from occurring during the mode transitions.

Semiconductor memory device having a burn-in control circuit and burn-in

Integrated circuit chips with fuse-based mode selection capability include a first signal generator for storing a first logic state when the fuse is blown, in response to an externally generated input signal, and for generating a first option changing signal based on the stored first logic state. To reduce the susceptibility to noise and inadvertent designation signals, a second signal generator for storing a second logic state when the fuse is blown is also provided and that fuse is blown in response another externally generated input signal. However, rather than blowing the fuses of the first option changing signal generator and the second option changing signal generator by applying external input signals simultaneously, the fuses are blown sequentially by connecting the second option changing signal generator in series with the first option changing signal generator so that the second option changing signal cannot be generated unless the first option changing signal generator has already been generated. To further lessen the likelihood of inadvertently blowing a fuse, thereby causing a reduction in yield of an integrated circuit semiconductor device, the first option changing signal generator is also connected in series with a dummy option changing signal generator. This dummy option changing signal generator is used to prevent the inadvertent generation of the first logic state caused by a blown fuse in the first option changing signal generator. The first and second option changing signals are then provided to a functional circuit to designate an active mode.

Integrated circuit devices with reliable fuse-based mode selection

Semiconductor integrated circuits, and more particularly an internal power-supply voltage supplier, can be adapted to high density memory devices, for providing a converted external power-supply voltage as an internal power-supply voltage having a desired potential. An internal power-supply voltage supplier receives a reference signal and an internal power-supply voltage signal and provides a semiconductor integrated circuit with an internal power-supply voltage having a desired voltage level by way of a driver, and comprises an offset generator connected to the driver, including two transistors having different width-length characteristics, for receiving the reference signal and the internal power-supply voltage signal and producing an offset corresponding to the received signals, the internal power-supply voltage is provided at a desired voltage level by the driver when the offset generator performs an offset operation.

Internal power-supply voltage supplier of semiconductor integrated

A decoding circuit and method for a semiconductor memory device simplifies a decoding process by individually performing a large block decoding and small block decoding operations, and thereby reduces the total time delay taken in an address decoding process and layout area occupied by decoding circuits. The decoding circuit for a semiconductor memory device having a memory cell array including a plurality of large blocks, each large block including m small blocks (wherein m=2,3, . . . ) and having a plurality of memory cells being arranged in a matrix form, and a plurality of reading/writing circuits each corresponding to said large blocks, includes a first decoding circuit for receiving a first address to simultaneously select respective specific small block in each of the large blocks, corresponding to the first address, and a second decoding circuit for receiving a second address to enable a selected one of the reading/writing circuits corresponding to said second address.

Growing community of inventors

Seoul, South Korea

Hee-Choul Park