Nepes Co., Ltd.

The Industry & Academic Cooperation in Chungnam National University

Sts Semiconductor & Telecommunications Co., Ltd.

Renewable Energy Platform Co., Ltd.

Hee Cheol Kim

Yong Tae Kwon

Sang Ho Lee

Hyun Sik Kim

Jae Hyun Yoo

Seung Wan Song

Young Seok Lee

Seung Jun Moon

Dong Hoon Seo

Seung Hwan Shin

Quang Hieu Pham

Ji Hee Jang

Eui Hyeong Hwang

Jini Shim

Dong Soo Lee

Younggil Kwon

The present invention relates to a lithium secondary battery electrolyte and a lithium secondary battery including the same and, more specifically, to a flame retardant or nonflammable lithium secondary battery electrolyte having excellent stability even at a high voltage and a lithium secondary battery including the same.

Electrolyte for lithium secondary battery and lithium secondary battery comprising same

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.

Semiconductor package

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

Semiconductor package and method of manufacturing same

Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in a position, in which a semiconductor chip is to be attached, of the patterned wafer through an etching process, fixing the semiconductor chip to the interior of the recess, and applying a passivation material to portions other than the semiconductor chip within the recess and to an upper end of the wafer. The wafer level package includes a silicon or glass wafer including a recess formed through etching and having an area larger than a semiconductor chip, a semiconductor chip fixed to the interior of the recess, and a passivation material filling an empty space other than the semiconductor chip within the recess and applied to a portion corresponding to an area larger than the semiconductor chip on an upper end of the wafer.

Fan-out wafer level package and manufacturing method thereof

Growing community of inventors

Cheonan-si, South Korea

Hee Cheol Kim