Samsung Electronics Co., Ltd.

Aptina Imaging Corporation

Hee-Cheol Choi

Seung-hoon Lee

Geun-Soon Kang

Kyung-Hoon Lee

Hai Yan

Kwang-Hee Lee

Young-Jae Cho

Eun-seok Shin

Dong-young Chang

You-Mi Lee

Sanghoon Lim

Hong-Joo Park

An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.

Imagers with improved analog-to-digital converters

In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.

Capacitor and capacitor array

A system and method for processing an input signal, such as an analog video input signal, are described. The system includes a correlated double sampler (CDS) for receiving an input signal, sampling the input signal and providing an output signal, the CDS comprising an amplifier for amplifying the input signal. The sampled and amplified output of the CDS is applied to a programmable gain amplifier (PGA). The PGA receives the output signal from the CDS and amplifies the received signal. By providing gain in both the CDS and the PGA, the system of the invention uses much smaller area than conventional systems. Also, a pseudo log scale gain response for the overall system is realized.

Apparatus and method for amplifying analog signal and analog preprocessing circuits and image pick-up circuits

A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current.

Circuits for generating reference current and bias voltages, and bias circuit using the same

The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2voltages and being arranged to be folded; a comparator array including (2&#x2212;1) comparators for comparing voltage differences between the respective 2voltages and an analog input signal to generate a digital thermometer code having (2&#x2212;1) bits and an encoder for encoding the digital thermometer code having (2&#x2212;1) bits to generate an n-bit digital signal. The layout method of the flash type analog to digital converting circuit comprises arranging the comparators such that the comparators of (2&#x2212;1)comparator to (2/2)comparator are arranged in order and the comparators of (2/2&#x2212;1)comparator to a first comparator are arranged in reverse fashion between the comparators of the (2&#x2212;1)comparator to the (2/2)comparator; and arranging the comparators such that the neighboring comparators adjacent to the respective (2&#x2212;1) comparators remain at to the same state when the (2&#x2212;1)comparator to the (2/2)comparator transit to different states respectively. Therefore, increasing of an offset voltage due to the effects of the neighboring comparators is prevented without increasing a layout area size.

Layout method of a comparator array for flash type analog to digital converting circuit

Multiplying Digital-to-Analog Converters (MDAC) multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal to produce an analog output signal at an output terminal. The MDACs include unit capacitors and a feedback capacitor. The unit capacitors are connected to the analog input terminal during a first time interval and the unit capacitors are selectively connected to a first reference voltage, a second reference voltage or the output terminal during a second time interval in response to the digital input signal at the digital input terminal. The feedback capacitor is connected to the second reference voltage during the first time interval and to the output terminal during the second time interval.

Multiplying digital-to-analog converters and methods that selectively connect unit and feedback capacitors to reference voltages and feedback voltages

Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

CMOS operational amplifiers having reduced power consumption

A binary-weighted capacitor array is applicable for use in analog-to-digital or digital-to-analog converters, switched-capacitor filters, etc. A plurality of unit capacitors are arranged in a lateral row. The row is laid out in parallel to a switch array so that each metal interconnect between a unit capacitor and a corresponding switch is of a uniform length. This layout eliminates several limitations commonly found in capacitor arrays, including: top-plate parasitic error due to metal interconnections and metal overlap; ratio error due to oxide thickness gradients; and edge-definition errors.

Growing community of inventors

Suwon-si, South Korea

Hee-Cheol Choi