Samsung Electronics Co., Ltd.

Yonsei University

Hee Chai Kang

Dong Hwan Lee

Won Seok Lee

Seong Ook Jung

Jong-Ryun Choi

Alex Joo

Kyeong Ho Ryu

A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.

Delay locked loop, electronic device including the same, and method of operating the same

Growing community of inventors

Namwon-si, South Korea

Hee Chai Kang