Samsung Electronics Co., Ltd.

Hee Bum Hong

Yongrae Cho

Seolun Yang

Lak Gyo Jeong

Lakgyo Jeong

Yong Rae Cho

Heesung Shin

Hojoon Lee

Kyo Wook Lee

Younghun Jung

Chang-min Hong

Seol Un Yang

Chang Min Hong

A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.

Semiconductor memory device and method of fabricating the same

Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

Semiconductor memory device including multiple conductive line layers

A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.

Method of manufacturing a semiconductor device

A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second region being a peripheral circuit region, first gate structures in a first direction on the first region and being spaced apart from each other in a second direction, second gate structures in the first direction on the second region and being spaced apart from each other in the second direction, the first and second gate structures being aligned with each other, a first insulating structure in the second direction on the buffer region between the first and the second regions along an entire length of each of the first and second regions in the second direction, and a second insulating structure on the first region and in contact with a part of the plurality of first gate structures.

Semiconductor device

Semiconductor device and method for manufacturing the same

A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.

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Hwaseong-si, South Korea

Hee Bum Hong