Escom Ag

Amiga Development LLC

Hedley Davis

A method and apparatus are provided for bidirectionally transmitting a plurality of data values between a first processor and a second processor. Each data value represents a respective plurality of data bits. A direction indicating signal is formed and transmitted from the first processor to the second processor. The direction indicating signal enables the second processor to transfer data to the first processor when the direction indicating signal is in a first state. The direction indicating signal notifies the second processor that the first processor is ready to transfer data to the second processor when the direction indicating signal is in a second state. A clock signal is formed and transmitted from the first processor to the second processor. The clock signal is asynchronously changed from a first state to a second state when each respective one of the plurality of data values is transferred. The data values are transmitted between the processors in a direction indicated by the direction indicating signal. The clock signal is reset to the first state after each respective data signal is transferred.

Bidirectional data transfer protocol primarily controlled by a peripheral device

A data processing system including a buffer memory having a plurality of segments for storing data and a memory location pointer having a plurality of bits, where each of the memory location pointer bits corresponds to a respectively different one of the buffer segments. The data processing system includes a central processing unit that writes binary data values into the memory location pointer to indicate availability of each of the buffer segments. A direct memory access controller unit continually transfers blocks of data from a mass storage device into the available buffer segments as indicated by the memory location pointer. The DMA controller further changes the state of the binary values, corresponding to the segments into which the blocks of data were stored, to indicate that the segments are not available for data transfer. The data processing system identifies each block of data, as it is stored in different buffer segment locations, to match the transferred block of data to the requests for data from the storage device.

Apparatus for selectively loading data blocks from CD-ROM disks to

A circuit which transforms image data between bit-plane data representations and multi-bit pixel representations includes a plurality of sequential logic elements arranged as a matrix having columns and rows. Data values representing bit-plane data are stored into the columns of the matrix according to a first scheme and data values representing multi-bit pixel data are stored into the columns of the matrix according to a second scheme. Data applied to the columns of the matrix is shifted along the rows until the matrix is filled. The converted data is then read out along the rows of the matrix.

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Freemont, CA, United States of America

Hedley Davis