Etat Francais Represente Par Le Ministre Delegue Des Postes Et

Etat Francais, Represente Par Le Ministres Delegue Des Postes Et

Hedi Hmida

Pierre Duhamel

A binary multiplier circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced. A fixed operand is multiplied by a variable operand by storing a partial result of the multiplication using an accumulator and a shift register with the binary calculation circuit. A two-input multiplexer has one of its inputs connected to the output from the register and an output connected to the input of the register. The variable operand is applied serially to a control input of the multiplexer.

Binary multiplier circuit with improved inputs

A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.

Binary adder circuit with improved inputs

A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai.sym.Bi) is produced by inverting the two input bit exclusive-OR signal (Ai.sym.Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).

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