Texas Instruments Corporation

Hector Torres

Charles Parkhurst

Ricky Dale Jordanger

Mark William Morgan

Steven J Tinsley

Yanli Fan

Kevin William Ziemer

Ramlah Binte Abdul Razak

Julie Hwang

Mark Bryan Hamlyn

Joao Carlos Felicio Brito

Lawrence James Gewax

Javier Antonio Valle Mayorga

A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.

Ceramic semiconductor device package with copper tungsten conductive layers

A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.

Chopper stabilized attenuation for sense amplifiers

A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.

Ceramic package opening, heat sink, vias coupled to conductive pad

A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short

Driver and slew-rate-control circuit providing soft start after recovery from short

An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.

Multiple chip synchronization via single pin monitoring of an external timing capacitor

A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between the upper and lower rails and the second leg includes third and fourth N-type transistors coupled in series between the upper and lower rails. The size of the first N-type transistor is (Y&#xb7;A), the second N-type transistor is (X&#xb7;A), the third N-type transistor is (X&#xb7;A) and the fourth N-type transistor is (Y&#xb7;A) where X and Y are integers and Aand Aare the sizes of respective reference transistors. A fuse has a first terminal coupled between the first and second N-type transistors and a second terminal coupled between the third and fourth N-type transistors; a first control node on the second leg of the current minor is coupled to control the voltage at an output node of the fuse cell.

Zero bias fuse cell

Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter includes two current sense element/current clamp control loops. A fast response time control loop first engages and clamps a current spike. A precision control loop then engages to more accurately clamp the output current to a programmed set point. The precision clamping loop includes an inner loop to linearize the precision current sense element. The inner loop forces the drain-to-source voltage (VDS) of the precision sense element to track the VDS of the regulator pass element. A more precise clamping operation results. Overall speed is not sacrificed as the fast response time clamping loop operates in parallel to protect circuitry while the precision clamping loop engages.

Fast transient precision power regulation apparatus

An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.

Reducing common mode transconductance in instrumentation amplifiers

A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.

High speed fully differential resistor-based level formatter

An apparatus for regulating voltage for at least one differential transistor pair having a voltage follower buffer, the voltage follower section having a first voltage-temperature response, includes: (a) a differential amplifier having two input loci and an output locus, a first input locus of the two input loci receiving a reference voltage; (b) a temperature responsive unit coupled between the output locus and ground; and (c) a feedback line coupled between the temperature responsive unit and a second input locus of the two input loci. The temperature responsive unit has a second voltage-temperature response similar to the first voltage-temperature response.

Apparatus for regulating voltage

A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of differential inputs and at least one differential output. The multiplexor includes a plurality of transmission gates to allow any one of the differential inputs to be routed to any differential output. Each transmission gate includes a first PMOS transistor and an NMOS transistor. The multiplexor further includes first Schottky diodes coupled between Vcc and the back-gate nodes of the first PMOS transistors, and second PMOS transistors coupled as shunts between the gate nodes of the first PMOS transistors and the source nodes of the NMOS transistors. The first Schottky diodes block the back-gate diode-to-Vcc leakage current paths and the second PMOS transistors block the leakage current paths from the differential inputs to the first PMOS transistors when the input voltage exceeds Vcc.

Input current leakage correction for multi-channel LVDS front multiplexed repeaters

An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at least one predetermined format. The apparatus includes: (a) at least one input locus coupled with each input channel for receiving the signals; (b) at least one output locus for presenting selected communication signals in a desired format in at least one output channel; and (c) a plurality of treating circuits for treating the signal excursions in a plurality of formats that include the predetermined format and the desired format. Each treating circuit is coupled with at least one respective input locus and at least one respective output locus. The apparatus presents sufficiently low capacitance between input loci and output loci to impart substantially zero time delay to the communication signals.

Apparatus for handling high speed data communication signals and method for manufacture thereof

A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage V rises, the predrive output voltage is lowered in response.

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McKinney, TX, United States of America

Hector Torres