International Business Machines Corporation

Hector Saenz

Daniel Mark Dreps

Seongwon Kim

Daniel Joseph Friedman

Michael Sperling

Robert J Reese

Frank David Ferraiolo

Glen Arthur Wiedemeier

Paul David Muench

Norman Karl James

Peter Matthew Thomsen

Paul Gordon Robertson

A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.

Delay line regulation using high-frequency micro-regulators

A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple digitally selectable inputs are included in the current reference circuit and are coupled to the current source circuit. These inputs are used to adjust a value of the current reference output.

Digitally tunable high-current current reference with high PSRR

Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Programmable delay element

CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Power supply noise insensitive multiplexer

Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry

Delay circuits have programmable delay elements to delay data signals so a clock samples the data signals in the middle of the eye window pattern. The clock is frequency divided by two, generating a divided clock coupled to a clock delay circuit and a data delay circuit generating a toggle clock and a delayed toggle clock that are sampled with the clock signal. A state machine varies the number N of delay elements selected in the data delay circuit until successive samples of the toggle clock and the delay toggle clock have opposite logic stages. The resulting number N is the number of delay elements required to generate a delay equal to one period of the clock. The delay of each delay element is adjusted using adjustment control signals until an N is generated that is within a predetermined range. The adjustment control signals are distributed to the data delay circuits.

Circuit for optimizing a delay line used to de-skew received data signals relative to a received clock signal

An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port are provided. The apparatus and method include a permanent connection port and a transient connection port located at the rear of a rack mounted server system and the front of the rack mounted server system, respectively. The permanent connection port operates when there is an absence of a connected device at the transient connection port. When a device is connected to the transient connection port, a signal is sent to a logic switch which causes the active input to be switched from the permanent connection port to the transient connection port. When the device is no longer connected to the transient connection port, the absence of the signal from the transient connection port causes the logic switch to switch the active input back to the permanent connection port.

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Round Rock, TX, United States of America

Hector Saenz