National Instruments Corporation

Hector M Rubio

Garritt W Foote

Rafael Castro Scorsi

Gerardo Daniel Domene-Ramirez

Kunal H Patel

Andrew Michael Lynch

Ashish S Chaudhari

Patrick Karl Sisterhen

Daniel Domene

Antonia Marie Walls Jones

Daniel Paul Jepson

Klaus Martin Braun

Moritz Daniel Fischer

Systems and methods for communication between heterogenous processors via a virtual network interface implemented via programmable hardware and one or more buses. The programmable hardware may be configured with a multi-function bus such that the programmable hardware appears as both a network device and a programmable device to a host system. Additionally, the programmable hardware may be configured with a second bus to appear as a network device to an embedded system. Each system may implement network drivers to allow access to direct memory access engines configured on the programmable hardware. The configured programmable hardware and the network drivers may enable a virtual network connection between the systems to allow for information transfer via one or more network communication protocols.

Programmable hardware virtual network interface

A system may include a data acquisition hardware device (DAQ) for acquiring sample data and/or generating control signals, and a host system with memory that may store data samples and information associated with the DAQ and host system operations. The DAQ may push hardware status information to host memory, triggered by predetermined events taking place in the DAQ, e.g. timing events or interrupts. The DAQ may update dedicated buffers in host memory with status data for any of these events. The pushed status information may be read in a manner that allows detection of race conditions, and may be used to handle data acquisition, output control signaling, and interrupts as required without the host system having to query the DAQ. The DAQ may also detect data timing errors and report those data timing errors back to the host system, and also provide improved output operations using counters.

Methods for data acquisition systems in real time applications

A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device.

Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample.

Phase aligned interleaved sampling of multiple data channels

Provided is a system for generating coefficient values. The system may include a base function generator and a series of accumulators including a leading and a last accumulator. In the series of accumulators, the data output of each accumulator, except the last, may be coupled to the data input of a successive adjacent accumulator. The base function generator may be configured to output, to the leading accumulator, a series of data values that may correspond to a base function that is a specified order derivative of a filter function. Each accumulator may be configured to: add a data value currently at its data input to a currently stored data value to produce an updated data value that may correspond to a respective value of a specified order integral of the base function; store the updated data value in the accumulator; and output the updated data value at its data output.

Generating filter coefficients for a multi-channel notch rejection filter

A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.

Integrated digitizer system with streaming interface

Phase aligned sampling of multiple data channels using a successive approximation register converter

A system for processing sample sequences, that may include an input, a sequence of coupled registers, including an accumulator register, and first circuitry that may be coupled to the accumulator register and to the input. The input may be configured to receive a first number of sample sequences having two or more samples. To process the first number of sample sequences, the first circuitry may be configured to generate a current effective sample corresponding to the sample for each sample in each sample sequence, write the current effective sample to the accumulator register, and shift the contents of each register into a successive register in the sequence of registers. After processing, each register of at least a subset of the sequence of registers may hold a respective final effective sample that may correspond to a different position in a processed sample sequence.

Performing multiplication for a multi-channel notch rejection filter

Provided is a method for performing analog to digital conversion of a plurality of analog signal channels. The method may comprise successively processing each analog signal channel of a plurality of analog signal channels. The processing of an analog signal channel of the plurality of analog signal channels may comprise: selecting the analog signal channel from the plurality of analog signal channels, generating an analog output signal corresponding to an analog input signal transmitted over the selected analog signal channel, and sampling the analog output signal using a successive approximation register (SAR) converter. Sampling the analog output signal using a SAR converter may comprise sampling the analog output signal a specific number of times to produce a respective plurality of digital samples corresponding to the selected analog input signal.

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Austin, TX, United States of America

Hector M Rubio