Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Other

Hector Adrian Sanchez

Gayathri Bhagavatheeswaran

Xinghai Tang

Kathleen C Yu

Joshua Siegel

Jose M Alvarez

Khoi Mai

Lipeng Cao

Byoung W Min

Carlos A Greaves

Michael A Mendicino

Jim P Nissen

Ravindraraj Ramaraju

Kumar Abhishek

David R Bearden

Janos Farkas

Srikanth Jagannathan

Yeong-Jyh Tom Lii

Gianfranco Gerosa

Kirk J Strozewski

Lakshmikant Mamileti

Carmine Nicoletta

Ross D Philip

Leo Mathew

Michael Alan Sadd

Shayan Zhang

Alexander Hoefler

Andrew Christopher Russell

Kenneth R Burch

Anis Mahmoud Jarrar

Thomas Henry Luedeke

Charles Eric Seaberg

James Andrew Welker

Bradley J Garni

Eric F Drake

Arvind Raman

Tommi M Jokinen

Zhonghai Shi

Mohamed S Moosa

Harold Sreshta

Joseph Gergen

Sriram Kalpat

Christopher James Micielli

Neerali Janubhai Desai

Venkataram Mooraka

Kuo-Hsuan Meng

Sunitha Manickavasakam

Chai-Chin Chao

Stephen Robert Traynor

Khoi B Mai

Gayathri A Bhagavatheeswaran

A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.

Very low voltage I/O circuit and method for screening defects

An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

Integrity monitoring for input/output (IO) circuits of a system on a chip (SOC)

Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

IO analog rail control circuit for power ramps

A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Multivoltage high voltage IO in low voltage technology

A circuit with a first transistor includes a first current electrode coupled to a first voltage supply, a second current electrode coupled to a first circuit node, and a gate electrode coupled to receive a first input signal. A second transistor includes a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a gate electrode coupled to receive a first bias voltage. A third transistor includes a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a second circuit node, and a gate electrode. A fourth transistor includes a first current electrode coupled to the second circuit node, a second current electrode coupled to a third circuit node, and a gate electrode coupled to receive a second bias voltage. The gate electrode of the third transistor is coupled to the third circuit node. A fifth transistor includes a first current electrode coupled to the third circuit node, a second current electrode coupled to a second voltage supply terminal, and a gate electrode coupled to receive a second input signal.

High voltage integrated circuit devices with hot carrier injection damage protection

An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Embedded continuity test circuit

A circuit includes a plurality of voltage supply terminals including a lowest voltage supply terminal, an N-type finFET, and a current path electrically coupled to the lowest voltage supply terminal, where the N-type finFET transistor is located in the current path. The N-type finFET transistor includes at least one semiconductor fin, a gate structure made of a gate material located over the at least one fin, an end structure of the gate material located over an end of the at least one fin, a source electrode, and a drain electrode. The at least one fin is located over a well region, and the end structure is electrically tied to the well region, in which the well region is not electrically tied to the lowest voltage supply terminal.

Integrated circuit with finFETs having dummy structures

A receiver is provided. The receiver includes a first plurality of transistors configured and arranged as diodes connected in series and coupled between an input terminal and an output terminal. A first transistor of the first plurality is configured and arranged for receiving a signal at the input terminal having a voltage exceeding a voltage rating of the first transistor. A second plurality of transistors is configured and arranged as diodes connected in series and coupled between the output terminal and a voltage supply terminal. A second transistor includes a first current electrode coupled to a control electrode and a first current electrode of the first transistor and a control electrode coupled to a voltage source terminal. A third transistor includes a first current electrode coupled to a second current electrode of the second transistor at a first node. A fourth transistor includes a first current electrode coupled to a second current electrode of the third transistor and a second current electrode coupled at the output terminal.

High voltage tolerant receiver

A receiver is provided. The receiver includes a first signal path and a second signal path coupled between an input terminal and an output terminal. A first transistor in the first signal path has a control electrode coupled to a voltage source terminal and a first current electrode coupled at the input terminal. The first transistor is configured and arranged for receiving a first signal at the first input terminal having a voltage exceeding a voltage rating of the first transistor. A second transistor in the first signal path has a first current electrode coupled to a second current electrode of the first transistor and a control electrode coupled to receive a first control signal. The second transistor is configured to form an open circuit in the first signal path when the first control signal is at a first state. A first resistor network in the second signal path is configured and arranged for attenuating the first signal.

Receiver with configurable voltage mode

Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.

Integrated circuitry and methods for reducing leakage current

A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

System and method for enhanced clocking operation

Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

Temperature sensor circuitry with scaled voltage signal

A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.

Method and apparatus for a tunable driver circuit

Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Memory interface receivers having pulsed control of input signal attenuation networks

A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and a plurality of capacitors. The first and second drive transistors coupled to the last inverter of the first and second pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment, a plurality of discharge circuits is coupled to the first plurality of series-connected inverters. Another embodiment includes a combination of capacitors and discharge circuits coupled to the first plurality of series-connected inverters. The embodiments provide a driver circuit with high frequency voltage regulation.

Driver circuit receiving a regulated pre-driver supply voltage

Growing community of inventors

Houston, TX, United States of America

Hector Adrian Sanchez