Globalfoundries Inc.

International Business Machines Corporation

Heather M Truax

Stephen Peter Ayotte

Timothy M Sullivan

Glen E Richard

David J Hill

John Thomas Kinnear, Jr

Jared P Yanofsky

Benjamin J Pierce

Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.

Visually detecting electrostatic discharge events

An approach for detecting sudden changes in acceleration in a semiconductor device or semiconductor package containing the semiconductor device is disclosed. In one embodiment, a piezoelectric sensor is embedded in a semiconductor die. The piezoelectric sensor is configured to sense a mechanical force applied to the semiconductor die. An excessive force indicator is coupled to the piezoelectric sensor. The excessive force indicator is configured to generate an excessive force indication in response to the piezoelectric sensor sensing that the mechanical force applied to the semiconductor die has exceeded a predetermined threshold indicative of an excessive mechanical force.

Detecting sudden changes in acceleration in semiconductor device or semiconductor packaging containing semiconductor device

Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip).

Chip carrier with dual-sided chip access and a method for testing a chip using the chip carrier

Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

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Burlington, VT, United States of America

Heather M Truax