Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

He-Zhou Wan

Ching-Wei Wu

XiuLi Yang

Kuan Cheng

Ming-En Bu

Hung-Jen Liao

Hau-Tai Shieh

Yi-Tzu Chen

Fu-An Wu

Wenchao Hao

Luping Kong

Mengxiang Xu

Zong-Liang Cao

Xiu-Li Yang

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Circuit and method of operating the same

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

Latch circuit and memory device

A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Memory circuit and method of operating the same

A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

Shared decoder circuit and method

A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.

System and method of power management in memory design

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Hsinchu, Taiwan

He-Zhou Wan