Texas Instruments Corporation

He Lin

Manoj K Jain

Yunlong Liu

Jiao Jia

Sameer P Pendharkar

Zhipeng Feng

Andy Strachan

Lily Springer

Dening Wang

Alfred J Griffin, Jr

Gang Xue

Kun Chen

Chao Wu

A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

Superlattice photo detector

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

Trench capacitor with warpage reduction

A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Integrated trench capacitor formed in an epitaxial layer

In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

Zero capacitance electrostatic discharge device

A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.

Zero capacitance electrostatic discharge devices

A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.

Contact array optimization for ESD devices

Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.

Growing community of inventors

Frisco, TX, United States of America

He Lin