Cirrus Logic Inc.

Other

He Du

Zhongxuan Zhang

Yun-Ti Wang

A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, a biasing circuit for providing a bias voltage to each of the voltage controlled inverting delay cells, and a source-follower transistor for providing a control voltage to the biasing circuit and voltage controlled inverting delay cells. Each of the voltage controlled inverting delay cells includes a first and a second plurality of transistors which define two outputs of the voltage controlled inverting delay cell, and a clipper transistor connected between the two outputs to short them together whenever a difference between a bias voltage provided to a gate of the clipper transistor by the biasing circuit and a voltage on either one of the two outputs exceeds a threshold voltage of the clipper transistor. The biasing circuit includes a third plurality of transistors which are matched with corresponding ones of the first and second pluralities of transistors and the clipper transistor such that the bias voltage generated by the biasing circuit automatically changes so as to be substantially equal to voltages corresponding to a HIGH logic state on the two outputs of each voltage controlled inverting delay cell as the control voltage provided to the biasing circuit and each of the voltage controlled inverting delay cells changes.

High frequency differential VCO with common biased clipper

A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, and a plurality of transistors for providing control voltages to the plurality of voltage controlled inverting delay cells. Preferably, each transistor has a drain connected to a reference voltage, and a source connected to a voltage controlled inverting delay cell paired to that transistor. Consequently, each transistor acts as a source-follower so that it provides a control voltage to its corresponding voltage controlled inverting delay cell which follows a control voltage driving its gate, thereby isolating the control voltage provided to its corresponding voltage controlled inverting delay cell from power supply noise.

Voltage controlled oscillator including voltage controlled delay circuit

A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1and din2, and generates, in response to a first control signal .PHI..sub.1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal .PHI..sub.2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal .PHI..sub.0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, .PHI..sub.1 and .PHI..sub.2, is such that the second control signal .PHI..sub.2 is activated LOW after a finite period following the initial activation of the first control signal .PHI..sub.1 . The third control signal .PHI..sub.0 is preferably activated LOW when the first and second control signals, .PHI..sub.1 and .PHI..sub.2, are inactive HIGH.

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Sunnyvale, CA, United States of America

He Du