International Business Machines Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Hayden Cranford

Martin L Schmatz

Vernon Roberts Norman

Stacy J Garvin

Westerfield John Ficken

Joseph M Stevens

Todd Morgan Rasmus

Michael Raymond Trombley

Carrie Ellen Cox

David A Freitas

John Paul Rankin

Daniel P Greenberg

A time-interleaved SAR-ADC employs calibrated SAR-ADC circuits to convert sampled voltage levels into serial digital data. Variable delay clock circuits synchronize clock signals received at the respective SAR-ADCs to sampling points of analog serial data. IC and environmental fluctuations cause delay in the variable delay clock circuits to skew the clock signals. A calibrated SAR-ADC detects changes to the delays in the variable delay clock circuits. By delaying a first clock signal in the variable delay clock circuit, and comparing a phase of the delayed clock signal to a phase-shifted clock signal having a known phase shift relative to the first clock signal, a change in the delay of the variable delay clock circuit can be detected as a phase difference. Based on an indication of a phase difference, a delay control signal is generated to control the delay in the variable delay clock.

Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods

Circuits for a successive approximation register analog-to-digital converter and related methods. A global reference circuit includes a first super source follower (SSF) circuit having an input coupled to an output of a first current mirror and to a first adjustment circuit, and an operational amplifier having an input coupled to an output of the first SSF circuit and an output coupled to an input of the first current mirror. Local slices each include a second current mirror having an input coupled to the output of the operational amplifier, a second super source follower (SSF) circuit having an input coupled to an output of the second current mirror and to a second adjustment circuit. The first and second adjustment circuits may be configured to adjust a voltage at the input of the first SSF circuit and respective voltages at the input of the second SSF circuit of each local slice.

Temperature compensation for reference voltages in an analog-to-digital converter

A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Test circuit for serial link receiver

Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Serial link output stage differential amplifier and method

A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Transistor switch with integral body connection to prevent latchup

The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

Clock data recovering system with external early/late input

A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Serial link receiver with wide input voltage range and tolerance to high power voltage supply

The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

Growing community of inventors

Cary, NC, United States of America

Hayden Cranford