International Business Machines Corporation

Globalfoundries Inc.

Qualcomm Incorporated

Hayden C Cranford, Jr

Vernon Roberts Norman

Martin L Schmatz

Sebastian Theodore Ventrone

Joseph Andrew Iadanza

Anthony Richard Bonaccio

Steven Mark Clements

Carrie Ellen Cox

Igor Arsovski

Stacy J Garvin

Pradeep Thiagarajan

James Stephen Mason

Todd Morgan Rasmus

Gareth John Nicholls

Chih-Chao Yang

Louis Lu-Chen Hsu

Michael Anthony Sorna

Thomas Helmut Toifl

Fadi Hikmat Gebara

Jeremy Daniel Schaub

Todd Edwin Leonard

Westerfield John Ficken

Louis L Hsu

Terence B Hook

Stephen Dale Wyatt

Serafino Bueti

Steven Elliott Mikes

Joseph M Stevens

Marcel A Kossel

Geoffrey B Stephens

Minhan Chen

William Richard Kelly

Raymond Paul Rizzo

Hemen R Shah

Paul Alan Owczarski

Mohak Chhabra

William P Cornwell

Michael Chen

Oleg Gluschenkov

Daniel Mark Dreps

Daniel Joseph Friedman

Charles R Hoffman

Mounir Meghelli

Juan Antonio Carballo

Anthony K Stamper

Douglas Duane Coolbaugh

Thomas E Morf

Jonathan E Proesel

Karl David Selander

Joseph Natonio

Eugene R Atwood

James D Rockrohr

Steven John Zier

Huihao Xu

Matthew B Baecher

Brian Joel Schuh

Samuel Taylor Ray

Scott David Huss

Rashmi R Bindu

David William Boerstler

Jieming Qi

John Francis Bulzacchelli

Ram Kelkar

Steven John Baumgartner

David W Siljenberg

Christian I Menolfi

Jason Michael Norman

Anjali R Malladi

John Farley Ewen

Alfred Degbotse

Jonathan H Raymond

Peter Robert Seidel

Philip J Murfet

James Francis McElwee

Venkatasreekanth Prudvi

Michael Thomas Fertsch

Steven Howard Johnson

John M Mullen

Wentai Liu

John Joseph Bergkvist, Jr

Kenneth J Shaw

Martin B Lundberg

Jonathan Henry Raymond

Vivek K Sharma

William L Bucossi

Guneet Singh

Marc R Turcotte

Daniel P Greenberg

John K Koehler

Bobak Modaress-Razavi

Sandeep Tippannanavar

Carrie E Aust

Neelamekakannan Alagarsamy

Theodore Allen Gary

Joseph Ronald Efferson, Jr

Mark Edmund Scheuer

Gregg Kreielsheimer

Eirik Gude

Josep A Iadanza

Joseph A Iandanza

Methods according to the disclosure include methods for managing data flow in an optical communications system having a plurality of vertical cavity surface emitting lasers (VCSELs). The method generally includes determining whether operation of the system exceeds a thermal threshold for a thermal parameter of the system, and switching from a first data bandwidth to a second data bandwidth when the thermal threshold is exceeded. Operation at the second data bandwidth further includes determining whether further operation of the system demands the first data bandwidth, and resuming operation of the system at the first data bandwidth only when the thermal parameter during operation at the second data bandwidth does not exceed the thermal threshold.

Managing data flow in VCSEL-based optical communications system

Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLKand CLK), where the pulse rate of CLKis slower than that of the CLKand greater than that of CLK. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLKbased on CLKand N-phases of the CLKand a second multi-phase pulse generator can generate N-phases of CLKbased on CLKand N-phases of CLK. Furthermore, additional registers can optionally use the N-phases of CLKto further generate N sets of M-phases of the CLK. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods

Methods according to the disclosure include methods for controlling an optical communications system. The method may include adjusting a VCSEL transmitter of the optical communications system to operate at a second data bandwidth distinct from its first data bandwidth; reducing a data flow rate of a receiver during operation of the optical communications system at the second data bandwidth; determining whether a system quality metric for the receiver meets a specification requirement; in response to determining the system quality metric does not meet the specification requirement, adjusting an operational setting of the VCSEL transmitter or the receiver; in response to determining the system quality metric meets the specification requirement, continuing operation of the optical communications system at the second data bandwidth; and in response to receiving an override signal, resuming operation of the optical communications system at the first data bandwidth.

Control of VCSEL-based optical communications system

A circuit including: input and output nodes and first and second feedback nodes; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a capacitor connecting the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier with an input connected to the output node and an output connected to the first feedback node; a tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for varying a transconductance of the tunable feedback circuit and operational frequency of the peaking amplifier circuit.

Peaking amplifier frequency tuning

A phase rotator apparatus has phase interpolation and transimpedance amplifier (TIA) stages. This separates gain and bandwidth as degrees of design freedom, facilitating a reduction in power consumption while enabling the data link to transmit and receive higher speed data. Four phases of an incoming signal are combined by the phase interpolation stage using weighting currents and current-source loads to produce a phase shifted current based signal that the TIA stage receives as input. The TIA stage then converts the signal to a voltage based signal. The quiescent operating voltage of the stage outputs can be maintained with common mode feedback circuits and injector currents.

Phase rotator apparatus

The disclosure is directed to a tunable peaking amplifier circuit including: an input node, an output node and a feedback node; a first input amplifier having an input connected to the input node and an output connected to the feedback node; a second input amplifier having an input connected to the input node; a coupling capacitor connected between an output of the second input amplifier and the feedback node; an amplifier having an input connected to the feedback node and an output connected to the output node; and a feedback circuit having an input coupled to the output node and an output connected to the feedback node, the feedback circuit including a tuning circuit for varying a transconductance of the feedback circuit to adjust an operational frequency of the peaking amplifier circuit.

A tunable peaking amplifier circuit including: an input node, an output node, and a feedback node; a first input amplifier having an input connected to the input node and an output connected to the feedback node; a second input amplifier having an input connected to the input node; a coupling capacitor connected between an output of the second input amplifier and the feedback node; an amplifier having an input connected to the feedback node and an output connected to the output node; a feedback circuit including: a base feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tunable feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tuning circuit for varying a transconductance of the feedback circuit to adjust an operational frequency of the peaking amplifier circuit.

A method and apparatus and computer program product for calibrating a Phase Lock Loop (PLL) that reduces a PLL lock time for subsequent calibrations to thereby improve an overall system time and latency. The system and method for calibrating obviates effect of Process, Voltage and Temperature to achieve a faster PLL lock.

System and method to speed up PLL lock time on subsequent calibrations via stored band values

A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Current mode logic circuit with multiple frequency modes

A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.

Systems for signal detection

Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.

Power aware equalization in a serial communications link

Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.

Systems and methods for signal detection

Testing a Decision Feedback Equalizer ('DFE'), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Testing a decision feedback equalizer ('DFE')

Growing community of inventors

Cary, NC, United States of America

Hayden C Cranford, Jr