Qualcomm Incorporated

Qualcomm Innovation Center, Inc.

Haw-Jing Lo

Dexter Tamio Chun

Michael Drop

Tao Xue

Moinul H Khan

Yanru Li

Christopher Kong Yee Chun

Steven S Thomson

Ali Iranli

Vinodh Ramesh Cuppu

Jungwon Suh

Hee Jun Park

Nhon Toai Quach

Stephen A Molloy

Mark Bapst

Jeffrey Gemar

Boris Andreev

Tauseef Kazi

Ali Taha

Vinod Chamarty

Aravind Bhaskara

Olivier Alavoine

Simon Booth

Alex Tu

Virat Deepak

Tao Shen

Edoardo Regini

Wenbiao Wang

Renatas Jakushokas

Sejoong Lee

Keunsoo Roh

Saurabh Patodia

Oscar Cabral Arias

Venkata Narayana Ramesh Pinnamaraju Durga

Julien Chaffraix

Su Zhao

Moinul H Kahn

Michael J Drop

Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns

Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Forced idling of memory subsystems

Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

System and method for conserving power consumption in a memory system

Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

Systems and methods for dynamically adjusting memory state transition timers

Various embodiments of methods and systems for temperature compensated memory refresh ('TCMR') of a dynamic random access memory ('DRAM') component are disclosed. Embodiments of the solution leverage a memory refresh module located within a memory subsystem to apply a refresh power supply received from a source on the SoC. Advantageously, even though the refresh power supply is received from a source on the SoC according to a certain delivery rate that may not be optimal for each and every bank in the DRAM component, embodiments of the solution are able to apply an effective refresh power supply rate to each bank according to its optimal cycle.

System and method for temperature compensated refresh of dynamic random access memory

Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Systems and methods for reducing volatile memory standby power in a portable computing device

Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

System and method for memory channel interleaving with selective power or performance optimization

Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

System and method for conserving memory power using dynamic memory I/O resizing

Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Method and apparatus for DRAM spatial coalescing within a single channel

Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

System and method for reducing memory I/O power via data masking

Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT&#x2212;PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Methods and systems for smart refresh of dynamic random access memory

Methods and devices for displaying content in a power efficient manner are disclosed. In accordance with many embodiments, content is received that includes a plurality of subcomponents, and a subcomponent with a larger surface is darkened so as to generate at least one darkened subcomponent. In addition, a contrast of selected ones of the subcomponents is adjusted so as to enable the selected ones of the subcomponents to be viewed against the darkened subcomponent while others of the plurality of subcomponents are left in their source format. The at least one darkened subcomponent, selected ones of the subcomponents, and the subcomponents that are in their source format are composited into a composite view; and displayed.

Method and apparatus for content-based reduction of display power

Various embodiments of methods and systems for hardware ('HW') based dynamic memory management in a portable computing device ('PCD') are disclosed. One exemplary method includes generating a lookup table (&#x201c;LUT&#x201d;) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

System and method for dynamic memory power management

Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

System and method of monitoring a central processing unit in real time

A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

Growing community of inventors

San Diego, CA, United States of America

Haw-Jing Lo