Fujitsu Corporation

Hatsuo Miyahara

Yoshihiro Takemae

Hirohiko Mochizuki

Shigeki Nozaki

Fumio Baba

Masao Nakano

Kimiaki Sato

Makoto Yanagisawa

Tsuyoshi Ohira

Katsuhiko Kabashima

Seiji Enomoto

Nobumi Kodama

Yasuhiro Takada

Masakazu Kanai

Satoshi Momozono

In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

Semiconductor integrated circuit having function for switching

A semiconductor device having a dynamic circuit and a static circuit, wherein a clock signal, in synchronization with the operation of the static circuit, initiates the operation of the dynamic circuit. A delay circuit of a static type is provided to delay the clock signal and generate a delayed clock signal. The delayed clock signal initiates operation of one stage of the dynamic circuit. As a result, the final-operation timing of the dynamic circuit is substantially controlled by the delayed clock signal, thereby matching the operation of the dynamic circuit with the operation of the static circuit, regardless of the power supply voltage.

Semiconductor device having matched-timing dynamic circuit and static

A semiconductor memory device operated synchronously with clock signals, such as a MOS dynamic RAM device. The semiconductor memory device includes a switch circuit inserted between a prestage output amplifier circuit receiving a readout signal from a memory cell and an output buffer circuit. The switch circuit is turned on just before the output signal is supplied from the prestage output amplifier circuit to the output buffer circuit and turned off after the output condition of the output buffer circuit is settled. The potential corresponding to the output data is maintained in the circuit between the switch circuit and the output buffer circuit. The output condition of the output buffer circuit is therefore retained even during the reset period of the prestage drive circuit, and the duration period of the output signal is expanded.

Semiconductor memory device

A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.

A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

Semiconductor integrated circuit device

A semiconductor memory device which includes a plurality of memory cells each having a capacitor, and peripheral circuits of the memory cells, integrated on a semiconductor substrate. Each capacitor has a storage electrode and an electrode opposite to the storage electrode, the opposite electrode being connected to a ground line, wherein, the ground line connected to the opposite electrode of each capacitor is separated from the other ground lines connected to the peripheral circuits. All of the ground lines are connected to a common portion having an impedance lower than the impedance of each ground line, whereby data stored in the capacitors is prevented from being destroyed.

A dynamic semiconductor memory device includes two bit lines connected to a sense amplifier and an active restore circuit which is formed from bit line pull-up transistors, each of which is connected between a bit line connected to the sense amplifier and a high potential source. In the active restore circuit, after the sense amplifier is actuated, the bit line pull-up transistor connected to the bit line on the high potential side is turned on by supplying a control signal to a gate so that the bit line is pulled up to a high voltage potential. The control signal is maintained at a voltage potential lower than the ground level from the time of actuation of the word line to the time of actuation of the sense amplifier.

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Yokohama, Japan

Hatsuo Miyahara