Kabushiki Kaisha Toshiba

Hatsuhiro Kato

Azuma Suzuki

Tomohiro Kobayashi

A synchronous-type memory performing in synchronization with a clock provided from an external device. This memory includes memory cells for storing data and selected by one of word lines, a decoder and a S/A. The decoder latches an address to select a word line in accordance with a rising edge of the clock, selecting a word line, and deselecting all word lines in accordance with a falling edge of the clock. The S/A stores the data transferred from the memory cell belonged to the word line selected by the decoder in synchronism with the rising edge of the clock before all the word lines is switched by the decoder to a deselected state, synchronized with the falling edge of the clock.

Synchronous-type memory

A BiNMOS inverter and a BiCMOS inverter are utilized. The BiNMOS inverter uses first and second power sources. A potential of the second power source is greater than that of the first power source. The BiNMOS has a first bipolar transistor whose collector being connected to the first power source and whose emitter being connected to an output node, and a first P-type field effect transistor group having at least one P-type field effect transistor through which a drain-source current channel consists of the base of the first bipolar transistor and the second power source based on an input signal transmitted to at lease one input node.

Semiconductor logic circuit using a first power source and a second

A reference current generator has a bipolar transistor Q1 having an emitter connected to a low-potential power source through a resistor R1, a bipolar transistor Q2 having a collector connected to the collector of the bipolar transistor Q1 and an emitter connected to the low-potential power source, and a bipolar transistor Q3 having a base connected to the bases of the transistors Q1 and Q2, an emitter connected to the low-potential power source, and a collector connected to a constant current source Io having negative temperature coefficient. The reference current generator provides a reference current Iref as the sum of a collector current of the bipolar transistor Q1 and a collector current of the bipolar transistor Q2. The reference current Iref may have a compensated, positive, or negative temperature coefficient as required.

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Hakodate, Japan

Hatsuhiro Kato