Cypress Semiconductor Corporation

Hatem Yazbek

Jeffery Scott Hunt

Christopher W Jones

George M Ansel

Jeffery Mark Marshall

A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

Power-on reset control circuit

A method and apparatus are disclosed for writing to a large content addressable memory (CAM) array without causing substantial power supply current surges, for providing fully static CMOS memory cells, for providing a consistent precharge of bit and bit bar lines, for providing a column write capability, and for increasing a read current while reducing a read disturbance probability. Each memory cell in the CAM array has (a) a data write circuit for accepting data, (b) a latch circuit for latching the data in the memory cell, (c) a hold circuit to allow holding the data or writing new data, (d) a data compare circuit for comparing the new data to the stored data, and (e) a data read circuit for reading the stored data. A memory cell further has control lines including (a) a read row enable (rren) line for enabling and disabling the data read circuit, (b) a match line for indicating a match between the stored data and the new data, (c) a write row enable (wren) line for enabling and disabling a row for a write operation, (d) a write column enable (wcen) line for enabling and disabling a column for a write operation, (e) a bit line, (f) a write column enable bar (wrenb) line for enabling and disabling the column for a write operation, and (g) a bit bar line. The present application also discloses methods for writing to CAM cells with a minimum power surge, for writing to a column of CAM cells, and for finding a match in the CAM array.

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Starkville, MS, United States of America

Hatem Yazbek