Skyworks Solutions, Inc.

Conexant Systems, Inc.

Atmel Corporation

Mindspeed Technologies, Inc.

Hassan S Hashemi

Siamak Fazelpour

Kevin J Cote

Roberto Coccioli

Mohamed A Megahed

Shiaw Wen Chang

Evan S McCarthy

Roger J Forse

Trang Trinh

Mahyar S Dadkhah

Thuy Tran

Robbie U Villanueva

Andrew Roman Gizara

Surasit Chungpaiboonpatana

Michael J Jarcy

Roberto U Villanueva

Khosrow Golshan

Mamdouh Atia

Igor Radutnuy

Evans S McCarthy

Surasit Chungpaibonnpatana

An antenna on integrated circuit (IC) package is disclosed. In an embodiment, an IC package comprises: a substrate; a radio frequency (RF) transceiver attached to the substrate; mold compound encapsulating the substrate; a shield layer formed on the mold compound; and one or more vias extending vertically through the shield layer and the mold compound, providing a conductive path to the RF transceiver. In another embodiment, a method comprises: attaching a radio frequency (RF) transceiver to a substrate; encapsulating the substrate with mold compound; forming a shield layer on the mold compound; and forming one or more vias through the shield layer and mold compound, providing a conductive path to the RF transceiver.

Antenna on integrated circuit package

Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bottom surface of the substrate. The disclosed embodiment further comprises at least one via in the substrate, which provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via also electrically connects a substrate bond pad and the printed circuit board. The substrate bond pad is further connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via further provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Method for fabricating a leadless chip carrier

An IC package includes a leadframe disposed within a mold body. A paddle is situated substantially on a first mold body surface. An outer paddle surface is substantially exposed for dissipating heat. A semiconductor die is coupled onto an inner paddle surface. A first portion of leads is formed against a side surface of the mold body for coupling to a PCB placed against a second mold body surface opposite to the first mold body surface. The footprint of the IC package is substantially coextensive with the footprint of the mold body. In another embodiment, an IC package includes a heat spreader having a semiconductor die attach area on an inner heat spreader surface between a first heat spreader end and a second heat spreader end. The heat spreader has insulator elements coupled to the ends of the heat spreader. The insulator elements can have bonding areas thereon.

Cavity down no lead package

Structure and method for fabrication of a leadless chip carrier

A semiconductor device is provided in the form of a chip carrier (e.g., chip/IC scale carrier for RF applications) that includes an integrated circuit chip attached to a die attach pad. The device has an interconnect substrate having an upper surface and a lower surface, with a plurality of vias passing through the thickness of the interconnect substrate from the upper surface to the lower surface. The die attach pad is located on the upper surface of the interconnect substrate, and a heat spreader is located on the lower surface of the interconnect substrate. A first group of vias is positioned to intersect both the die attach pad and the heat spreader. A second group of vias is positioned away from the die attach pad and the heat spreader. The upper surface has a plurality of bond pads that are abutting the second group of vias and the lower surface has a plurality of lands that are also abutting the second group of vias.

Leadless chip carrier design and structure

A multiple chip module (MCM) for use with baseband, RF, or IF applications includes a number of active circuit chips having a plurality of different functions. The active circuit chips are mounted on a substrate that is configured to provide an integrated subsystem in a single MCM package. The MCM includes a number of features that enable it to meet electrical performance, high-volume manufacturing, and low-cost requirements. The MCM may incorporate split ground planes to achieve electronic shielding and isolation, vias configured as both thermal sinks and grounding connections, and specifically configured die attach pads and exposed ground conductor pads.

Multiple chip module with integrated RF capabilities

One disclosed embodiment comprises a substrate having a top surface for receiving two or more semiconductor dies. The disclosed embodiment further comprises a printed circuit board attached to a bottom surface of the substrate and at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of a first semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a first substrate bond pad and the printed circuit board. The first substrate bond pad is connected to the first signal bond pad of the first semiconductor die by a first signal bonding wire. The at least one via also provides an electrical connection between the first signal bond pad of the first semiconductor die and a first land that is electrically connected to the printed circuit board.

Structure and method for fabrication of a leadless multi-die carrier

According to an embodiment, a semiconductor die has a source bond pad and a destination bond pad attached to a top surface of the semiconductor die. A stud bump is situated on the destination bond pad. A bonding wire is then ball bonded to the source bond pad and thereafter stitch bonded to the stud bump on the destination bond pad. The bonding wire acts as an off-chip inductor or a portion of an off-chip inductor. In one embodiment a number of bonding-wires and on chip conductors are used to form an off-chip inductor. The inductance of the off-chip inductor can be adjusted or fine-tuned by adjusting a loop height of the one or more bonding wires used in the off-chip inductor. The inductance of the invention's off-chip inductor can also be adjusted by increasing or decreasing the number of bonding wires used to form the off-chip inductor.

Off-chip inductor

According to one embodiment, a semiconductor die is situated in a cutout section of a substrate. In one embodiment, the substrate is situated on a printed circuit board such that the semiconductor die situated in the cutout section of the substrate is also situated on a support pad on the top surface of the printed circuit board. In one embodiment, a semiconductor die bond pad on the semiconductor die is connected to a substrate bond pad on the substrate. In one embodiment, an interconnect trace on the substrate is connected to an interconnect pad on the top surface of the printed circuit board.

Leadless chip carrier for reduced thermal resistance

Molded shield structures and method for their fabrication are disclosed. According to one embodiment, a die is attached to a printed circuit board, for example, by using a die attach epoxy. Thereafter, at least one post is attached to the printed circuit board adjacent to the die. The at least one post can be, for example, made of copper or solder-coated ceramic. A shield is then mounted on the at least one post. The shield encloses an area on the printed circuit board which includes the die and may include additional elements, such as passive devices. The shield can be, for example, made of stainless steel, copper, or a copper alloy. In one embodiment, the shield is a wire mesh which can be made of copper or aluminum. After mounting the shield, a molding compound is used to encapsulate the shield, the at least one post, the die, and any additional elements, such as passive devices, that are enclosed by the shield.

Molded shield structures and method for their fabrication

A leadframe includes at least one peripheral lead secured to a paddle. A paddle solder bump pad and a peripheral solder bump pad are respectively situated on the at least one peripheral lead and the paddle. A first recess is adjacent to the paddle solder bump pad and a second recess is adjacent to the peripheral solder bump pad. A semiconductor die having at least first and second solder bumps is situated on the leadframe such that the first solder bump is soldered to the paddle solder bump pad while the second solder bump is soldered to the peripheral solder bump pad. The first and second recesses adjacent to respectively the paddle solder bump pad and the peripheral solder bump pad prevent solder from flowing out of the solder bump pad areas during solder reflow process. In this manner, the potential shorting of adjacent solder bump pads is prevented.

Flip-chip leadframe package

One embodiment comprises a substrate having a top surface for receiving a semiconductor die. According to a disclosed embodiment, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second terminals to, respectively, a substrate signal bond pad and a semiconductor die signal bond pad. In another disclosed embodiment, an inductor is fabricated within the substrate. The inductor comprises via metal segments connecting interconnect metal segments on the top and bottom surfaces of the substrate. The first and second terminals of the inductor are easily accessible through first and second substrate signal bond pads. One embodiment comprises at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and a printed circuit board attached to the bottom surface of the substrate.

Leadless chip carrier with embedded inductor

In one embodiment, the invention includes first and second transmission lines fabricated in a redistribution layer over a semiconductor die. The first transmission line has a first distance from a first ground return path formed in a first metal level. The first transmission line has a first impedance corresponding to the first distance. In other words, the impedance of the first transmission line is affected by the distance between the first transmission line and the first ground return path. Similar to the first transmission line, the second transmission line has a second distance from a second ground return path formed in a second metal level. The second transmission line has a second impedance corresponding to the second distance. In other words, the impedance of the second transmission line is affected by the distance between the second transmission line and the second ground return path.

Controlled impedance transmission lines in a redistribution layer

An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

Voltage regulation for semiconductor dies and related structure

One disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die with a number of solder bumps on its active surface. The disclosed embodiment further comprises a printed circuit board attached to a bottom surface of the substrate. Another disclosed embodiment comprises at least one via in the substrate. The at least one via provides an electrical and thermal connection between a signal pad of the die and the printed circuit board. The at least one via provides an electrical connection between a substrate signal pad and the printed circuit board. The substrate signal pad is connected to the signal pad of the die by a signal solder bump. The at least one via also provides an electrical connection between the signal pad of the die and a land that is electrically connected to the printed circuit board.

Growing community of inventors

Laguna Niguel, CA, United States of America

Hassan S Hashemi