Motorola Corporation

Hassan Pirastehfar

Steven J Adler

Israel A Lesk

Robert Bruce Davies

George W Hawkins

David M Heminger

Gordon C Ma

George C Onodera

Stephen J Nugent

Waisiu Law

Peter L Pegler

A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.

Method of making a structure for top surface gettering of metallic

A field plate avalanche diode has a field plate extending over the breakdown PN junction.

Field plate avalanche diode

An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.

Double implanted laterally diffused MOS device and method thereof

A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

Low on resistance field effect transistor

An improved photo detector is provided by forming a tub of monocrystalline semiconductor material surrounded by a layer of monocrystalline material of opposite conductivity type. The improved structure is manufactured by means of a modified DIC process. The device may by made deep enough to absorb a large portion of the incident radiation near the PN junction without sacrificing a large number of photo-generated carriers to recombination.

Growing community of inventors

Mesa, AZ, United States of America

Hassan Pirastehfar