Shenzhen Goodix Technology Co., Ltd.

Goodix Technology Inc.

Hassan Osama Elwan

Ahmed Emira

Mohamed Aboudina

Ali Farid

Janakan Sivasubramaniam

Mengwen Zhang

Esmail Babakrpur Nalousi

Ahmet Tekin

An electronic circuit is disclosed. The electronic circuit includes a reference voltage generator, which includes a first candidate circuit configured to generate a first candidate reference voltage, a second candidate circuit configured to generate a second candidate reference voltage, and a selector circuit configured to select one of the first and second candidate reference voltages. The reference voltage generator also includes a third circuit configured to generate a power supply voltage based on the selected candidate reference voltage.

Voltage generator with multiple voltage vs. temperature slope domains

Techniques are described for implementing diodes with low threshold voltages and high breakdown voltages. Some embodiments further implement diode devices with programmable threshold voltages. For example, embodiments can couples a native device with one or more low-threshold, diode-connected devices. The coupling is such that the low-threshold device provides a low threshold voltage while being protected from breakdown by the native device, effectively manifesting as a high breakdown voltage. Some implementations include selectable branches by which the native device is programmably coupled with any of multiple low-threshold, diode-connected devices.

Diode with low threshold voltage and high breakdown voltage

An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Successive approximation register (SAR) analog to digital converter (ADC) with overlapping reference voltage ranges

A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.

Low-voltage reference current circuit

Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Peak-adaptive sampling demodulation for radiofrequency transceivers

A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.

Efficient successive approximation register analog to digital converter

An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.

Successive approximation register (SAR) analog to digital converter (ADC) with switchable reference voltage

A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

Data converters systematic error calibration using on chip generated precise reference signal

An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.

Successive approximation register (SAR) analog to digital converter (ADC) dynamic range extension

A current reference circuit includes a current source, a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source, and an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the drain of the first PMOS transistor. The current reference circuit also includes a first resistive element having a first terminal coupled to a source of the NMOS transistor and a gate of the first PMOS transistor and a second terminal coupled to a ground potential, a second PMOS transistor having a drain coupled to the first supply voltage, and a second resistive element having a first terminal coupled to the first terminal of the first resistive element and a second terminal coupled to the gate of the second PMOS transistor.

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San Diego, CA, United States of America

Hassan Osama Elwan