Broadcom Corporation

Sernai Networks, Inc.

Hassan Maarefi

Afshin Momtaz

Mahmoud Reza Ahmadi

Tamer Mohammed Ali

Ali Nazemi

Siavash Fallahi

Burak Catli

Bo Zhang

Heng Zhang

A wired communication system includes a bidirectional channel for sending information in one direction at a high bandwidth and sending control information for configuring a transmitter in the other direction at a lower bandwidth. Embodiments of the disclosure may use a primary transmitter output stage in the transmitter and a primary receiver input stage in the receiver to send and receive data or a clock, for example. An auxiliary transmitter output stage in the receiver and auxiliary receiver input stage in the transmitter send and receive control information for configuring the transmitter to efficiently send data over a wired channel.

High speed serializer-deserializer systems and methods

A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Method and apparatus for passive equalization and slew-rate control

A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

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San Jose, CA, United States of America

Hassan Maarefi