Newport Media, Inc.

Atmel Corporation

Hassan Elwan

Edward Youssoufian

Amr M Fahim

Dejun Wang

Frank Carr

Aly Mamdouh Ismail

Adel Fanous

Ahmed A Emira

Mohy Abdelgany

Ahmet Tekin

Edward Youssounan

An integrated circuit for digital controlling switching noise spurs in a receiver by shifting a switching frequency (f) to a clock frequency (f+&#x394;f) to move a Kharmonic of the switching frequency (f) is provided. The integrated circuit includes a spur controlled clock that operates the clock frequency (f+&#x394;f), and a DC-DC converter circuitry that includes a first power switch, and a second power switch. The first power switch and the second power switch are driven by the clock frequency (f+&#x394;f). &#x394;f ranges from and fis center frequency of a received channel. None of the harmonics of the clock frequency (f+&#x394;f) is present in a channel of interest. The switching frequency is larger than the channel bandwidth 2BW.

Digitally controlled spur management technique for integrated DC-DC converters

A method of filtering and a RF filtering circuit comprising a LO adapted to generate in-phase and quadrature LO signals; a quadrature passive mixer operatively connected to the LO; a filtering impedance operatively connected to the quadrature passive mixer, wherein the voltage at an input node of the quadrature passive mixer comprises the voltage across the filtering impedance up-converted to a frequency of a LO signal received by the quadrature passive mixer. Preferably, the voltage across the filtering impedance comprises a frequency of an input signal of the quadrature passive mixer down-converted by a frequency of the in-phase and quadrature LO signals and filtered by the filtering impedance.

System and method for performing RF filtering

A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.

Universal tuner for mobile TV

A portable memory device dimensioned and configured as any of a removable flash memory card, a USB flash drive, and a jump drive and a method of wireless communication, wherein the portable memory device comprises a single housing component; a data storage component within the single housing component; and a wireless receiver operatively connected to the data storage component and within the single housing component, wherein the wireless receiver is adapted to receive wireless signals comprising radio signals, satellite signals, TV signals, and Bluetooth&#x2122; specification signals, and wherein the wireless receiver is adapted to wirelessly communicate with a LAN. The portable memory device may further comprise an interface component adapted to connect to a host computing device. Preferably, the TV signals comprise mobile TV signals.

Device, system, and method for providing wireless data access, digital TV access, radio, and storage capability

An electrical circuit and method of power management of a cellular telephone includes a battery adapted to produce a battery voltage; a LDO regulator operatively connected to the battery and adapted to provide a constant supply voltage from the battery voltage; and a DC-DC converter operatively connected to the LDO regulator, wherein the DC-DC converter is adapted to step down the constant supply voltage to a lower voltage level, wherein the LDO regulator and the DC-DC converter are embedded on a single integrated circuit chip. The constant supply voltage equals 3.6V at an output of the LDO, and the constant supply voltage is applied to an input of the DC-DC converter. Moreover, the battery voltage equals at most 5.5V.

Integrated CMOS DC-DC converter implementation in low-voltage CMOS technology using LDO regulator

A continuous time sigma-delta analog-to-digital converter (CT &#x3a3;&#x394;ADC) including an integrator, which includes an operational amplifier having at least one input terminal that receives an input signal, a feedback mechanism operatively connected to the operational amplifier, at least one capacitor coupled to the operational amplifier and the feedback mechanism, a reset switch coupled to the at least one capacitor, the operational amplifier, and the feedback mechanism, and a single directional voltage-to-current converter coupled to the input terminal. The single directional voltage-to-current converter translates a differential signal voltage only to a differential signal current. The reset switch resets the feedback mechanism. The single directional voltage-to-current converter behaves a one-directional resistor. The integrator prevents current generation when there is a non-linear disturbance at the input terminal of the operational amplifier. The single directional voltage-to-current converter clips an input current that exceeds a threshold value.

Continuous time sigma-delta analog-to-digital converter with stability

A fully differential amplifier that amplifies and filters a signal band of a communications channel, the signal band including a desired signal and at least one blocker signal of an adjacent communications channel, the fully differential amplifier includes a fully differential operational amplifier (op-amp) with a common mode feedback, the fully differential operational amplifier amplifying the desired signal, a variable input resistance connected to an input of the fully differential op-amp, and an asymmetric floating frequency dependent negative resistance (AFFDNR) filter connected to the fully differential op-amp between the input and an output of the fully differential op-amp. A plurality of inputs of the fully differential op-amp may be virtually grounded to reduce swings in a voltage. The AFFDNR filter filters the at least one blocker signal and includes a plurality of resistors that implement a high order filtering of the at least one blocker signal.

Noise-shaped blocker-reject amplifier

A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

Low noise, low power, high linearity differential amplifier with a capacitive input impedance

A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.

Optimized gain filtering technique with noise shaping

A technique for downconverting a RF signal comprises an antenna adapted to receive an RF signal; a transconductance amplifier connected to the antenna and adapted to amplify the RF signal; a passive mixer connected to the transconductance amplifier and adapted for current domain mixing of electrical current transferred from the transconductance amplifier; and a load impedance connected to the passive mixer. The load impedance may comprise a parallel combination of a frequency dependent negative resistance component, a capacitor, and a resistor. The load impedance may comprise a pair of complex poles, a pair of imaginary zeros, and a real pole. Voltages at an input and an output of the passive mixer are related such that the input voltage of the passive mixer is an upconverted version of the output voltage of the passive mixer, wherein the input voltage of the passive mixer is at an output of the transconductance amplifier.

Low power highly linear RF downconverter

A portable memory device and method comprises a data storage component; and a wireless receiver operatively connected to the data storage component, wherein the wireless receiver is adapted to receive mobile TV signals. The portable memory device further comprises an interface component adapted to connect to a host computing device. The wireless receiver is adapted to receive radio signals. The wireless receiver is adapted to receive satellite signals. The wireless receiver comprises an antenna; a matching network operatively connected to the antenna; and a radio frequency (RF) receiver chip operatively connected to the matching network. The portable memory device further comprises a demodulator operatively connected to (or integrated in) the RF receiver chip. The data storage component comprises a flash memory unit comprising software code adapted to interface with a host computing device and process data on the host computing device.

Portable memory device and method

A continuous time-sigma delta (CT-SD) data converter comprising a loop filter includes a first integrator having a first loop filter coefficient and a second integrator operatively coupled to the first integrator, the second integrator having a second loop filter coefficient, a modulator coupled to the loop filter, a reset switch coupled to the second integrator, a first peak detector operatively coupled in series with the second integrator to indicate an instability condition of a signal level exceeding a first threshold at an output of the second integrator, a second peak detector adapted to detect an input signal level to the CT-SD data converter, and a digital engine coupled to the first peak detector.

Reconfigurable and adaptive continuous time-sigma delta data converter

A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.

Growing community of inventors

Lake Forest, CA, United States of America

Hassan Elwan