Semiconductor Components Industries, LLC

Hassan Chaoui

Pierre Andre Genest

Michael Bairanzade

In one embodiment, an amplification circuit receives an analog signal and adds another signal to the analog signal to modify the minimum amplitude of the analog input signal.

Amplification circuit and method therefor

In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Communication circuit and method therefor

In one embodiment, a current controller is configured to control a value of the current without regulating a voltage formed by the controller.

Current controller and method therefor

In one embodiment, a charge pump controller is configured with transistors having at least two different selectable on-resistance values may be used to charge a pump capacitor.

Method of forming a charge pump controller and structure therefor

In one embodiment, a class-D amplifier () is configured to form first (DP) and second (DN) PWM signals each having a duty cycle that is proportional to a received analog input signal () and responsively to enable a switch () to short the outputs () of the class-D amplifier () together responsively to some states of the first (DP) and second (DN) PWM signals.

Class-D amplifier and method therefor

In one embodiment, a charge pump converter is formed to use various values of an output voltage to selectively control a value of a charging current during a charging cycle of the charge pump converter.

Charge pump converter and method therefor

In one embodiment, a first portion () of translator circuit () is configured to extract a first supply voltage level from a high level of an input signal, an inverter () is configured to operate from the first supply-voltage level and a second portion () of the translator circuit is configured to operate from a second supply voltage level (V) that is greater than the first supply voltage level.

Method of forming a signal level translator and structure therefor

An RF detector ( ) is formed to compress the output voltage at two different rates depending on the value of the output voltage. Using two different rates of compression reduces saturation of the output voltage and reduces distortion. The RF detector ( ) also provides temperature compensation in the output voltage to reduce output voltage variations due to temperature changes.

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Toulouse, France

Hassan Chaoui